User`s guide

C.5 SIO PCI-to-ISA Bridge Conﬁguration Address Space

Table C–3 is a map of SIO PCI-to-ISA bridge conﬁguration address space.

PCI address bit pci_ad19 drives the idsel chip select pin for access to the

conﬁguration register space.

Table C–3 SIO PCI-to-ISA Bridge Conﬁguration Address Space Map

Offset Address Register

00–01 1 E008 0008 Vendor ID register

02–03 1 E008 0048 Device ID register

04–05 1 E008 0088 Command register

06–07 1 E008 00C8 Device status register

08 1 E008 0100 Revision ID register

40 1 E008 0800 PCI control register

41 1 E008 0820 PCI arbiter control register

42 1 E008 0840 PCI arbiter priority control register

44 1 E008 0880 MEMCS# control register

45 1 E008 08A0 MEMCS# bottom of hole register

46 1 E008 08C0 MEMCS# top of hole register

47 1 E008 08E0 MEMCS# top of memory register

48 1 E008 0900 ISA address decoder control register

49 1 E008 0920 ISA address decoder ROM block enable register

4A 1 E008 0940 ISA address decoder bottom of hole register

4B 1 E008 0960 ISA address decoder top of hole register

4C 1 E008 0980 ISA controller recovery timer register

4D 1 E008 09A0 ISA clock divisor register

4E 1 E008 09C0 Utility bus chip select enable A register

4F 1 E008 09E0 Utility bus chip select enable B register

54 1 E008 0A80 MEMCS# attribute register #1

55 1 E008 0AA0 MEMCS# attribute register #2

56 1 E008 0AC0 MEMCS# attribute register #3

57 1 E008 0AE0 Scatter-gather relocation base address register

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C–6 PCI Address Maps