User`s guide

B.1.8 Icache Flush Code

The following code is loaded into memory after the ﬂash ROM image. It is then

executed to ﬂush the SROM initialization code from the Icache. The SROM

initialization code is loaded into the Icache, and it maps to memory beginning

at address zero.

77FF0055 mt r31, flushIc

C0000001 br r0, +4

.long destination

6C008000 ldl_p r0, 0x0 (r0)

47FF041F bis r31, r31, r31

6BE00000 jmp r31, (r0)

In an attempt to transfer execution to the ﬁrst page in memory, execution

would continue in the SROM initialization code at that address. Therefore,

execution must be transferred to some address that does not hit in the Icache

where other code can ﬂush the Icache.

The NOPs following the Icache ﬂush allow the instructions that were fetched

before the Icache was updated to be cleared from the pipeline. Execution will

ultimately continue at the address contained in r0. At this point r0 contains

the starting address where the ﬂash ROM image was loaded into memory.

B.1.9 AlphaPC64 Conﬁguration Jumpers

The memory controller provides presence detect registers that contain the state

of the presence detect pins at reset. These pins reﬂect the SIMM presence

detect signals and the software conﬁguration jumpers. Refer to Appendix A.

The software conﬁguration jumpers are completely programmable. The SROM

code deﬁnes the software conﬁguration jumpers, sp_bit<7:0>, as shown in

Figure B–3 and deﬁned in Table B–8.

B–16 SROM Initialization