User`s guide

B.1.6 L2 Cache Initialization
These steps initialize L2 cache:
1. Set the BIU_CTL register in the CPU to ignore the L2 cache.
2. Set the general control register in the memory controller to enable the L2
cache while ignoring tag parity.
3. Clear the tag enable register in the memory controller.
4. Sweep the L2 cache with read transactions at cache block increments.
5. Reset the tag enable register with the proper value based on the L2 cache
and memory size.
6. Reset the general control register in the memory controller to disable the
ignore tag parity bit.
7. Reset the BIU_CTL register in the CPU with the proper value to enable
the L2 cache based on CPU speed, and L2 cache size and speed.
When the system is powered up, the L2 cache will contain UNPREDICTABLE
data in the tag RAMs. As the L2 cache is swept for initialization, the old
blocks (referred to as dirty victim blocks) will be written back to main memory.
These victim write transactions will occur based on the tag address that stores
the upper part of the address location for the dirty blocks of memory.
Because the tags are UNPREDICTABLE, the victim write transactions could
occur to UNPREDICTABLE addresses. Therefore, write transactions to
nonexistent memory could be attempted. If this happens, the transaction does
not complete and the tag is not updated in the cache.
By clearing the tag enable register, victim write transactions to nonexistent
memory are ignored. When the tag enable register is cleared, zero is always
stored in the tags. Tags of zero correspond only to the block of memory
beginning at zero up to the end of cache. Therefore, to initialize the cache,
only that memory range is swept with read transactions. Reading beyond that
memory range results in an incorrect tag address being stored.
SROM Initialization B–9