User`s guide

B.1.5 Memory Initialization

The memory banks must be conﬁgured such that they are naturally aligned.

For example, a bank conﬁgured with 32MB must have a base address of zero

or some multiple of 32MB. Therefore, to ensure that both banks are contiguous

(no gaps), the larger bank should be set to a base of zero, and the smaller bank

should be set to the address immediately following the last location in the

larger bank.

If the banks are the same size, this is still true. There is no requirement for

which bank must be the larger one. Therefore, the following algorithm is used

to determine the base addresses of the banks:

If bank_0_size bank_1_size

then

bank_0_base = 0

bank_1_base = bank_0_max_addr + 1

else

bank_1_base = 0

bank_0_base = bank_1_max_addr + 1

Eight consecutive RAS cycles are performed for each memory bank to ‘‘wake

up’’ the DRAMs. This is done by reading from each bank eight times. The

caches are disabled at this point so the read transactions go directly to the

DRAMs.

Good data parity is ensured by writing all memory locations. This is done

by rewriting the full contents of memory with the same data. Reading before

writing memory lengthens the time to initialize data parity; however, it

conserves the memory state for debugging purposes.

B–8 SROM Initialization