User`s guide
Write Cycle Calculations
WRsetup is the earliest from the beginning of a write cycle that the write pulse
can be asserted (see Figure B–1).
Figure B–1 Write Cycle Timing
LJ-04207.AI
WRpulse WRholdWRsetup
Taddress, based on the address path, and Tdata, based on the data path
determine the earliest from the beginning of a write cycle that the write pulse
can be deasserted. The larger of these two determine the more critical path on
which the write pulse is determined.
Because WRsetup is the earliest that the write pulse can be asserted, and
Taddress and Tdata determine the earliest that the write pulse can be
deasserted, it follows that:
:
The WRsetup requirement is offset by the write-enable path delay (WRhold),
and the WRhold requirement is offset by the address path delay (WRsetup).
The WRsetup and WRhold delays are then discounted by the fastest possible
delay through the other path. The minimum parameters estimate the absolute
fastest propagation through the address and write-enable paths.
Therefore:
SROM Initialization B–7