User`s guide

Table B–4 Worst-Case SRAM Timing Specifications
Typical SRAM Timing Specifications
Parameter
6-ns
SRAM
8-ns
SRAM
10-ns
SRAM
12-ns
SRAM
15-ns
SRAM
Tacc 6 ns 8 ns 10 ns 12 ns 15 ns
Twc 6ns 8ns 10ns 12ns 15ns
Twp 6 ns 8 ns 9 ns 10 ns 12 ns
Tdw 3 ns 4 ns 5 ns 6 ns 7 ns
Tdh 0 ns 0 ns 0 ns 0 ns 0 ns
Taw 6 ns 8 ns 9 ns 10 ns 12 ns
Twr 0 ns 0 ns 0 ns 0 ns 0 ns
Tas 0 ns 0 ns 0 ns 0 ns 0 ns
Table B–5 CPU Specifications
Function Specification Description
Tsu 3.5 ns Internal CPU setup time (21064A)
Tstable 2.9 ns CPU data stable time
B.1.4 L2 Cache Read and Write Calculations
The methods and equations for calculating L2 cache read and write timing are
presented in this section.
Read Cycle Calculation
B–6 SROM Initialization