User`s guide

Table B–2 Cache Loop Delay Characteristics
Function
Minimum
Delay
Maximum
Delay Description
Tadr1 1.0 ns 1.6 ns Delay from CPU to input of address buffer
Tbuf 1.0 ns 4.8 ns Buffer gate delay
Tadr2 1.2 ns 1.5 ns Address delay from buffer to SRAM inputs
Tdat NA
1
1.9 ns Data return path from SRAM to CPU
input pins
Twe1 1.0 ns 1.0 ns Delay from CPU to the NOR gate in the
WE path
Tnor 1.2 ns 5.0 ns NOR gate delay
Twe2 1.0 ns 1.0 ns Delay from the NOR gate to the SRAM
inputs
1
NA = Not applicable
Table B–3 SRAM Timing Specification Definitions
Parameter Definition
Tacc Access from address valid to data valid
Twc Write cycle time
Twp Write pulse width
Tdw Data setup to write pulse deassertion
Tdh Data hold from write pulse deassertion
Taw Address setup to write pulse deassertion
Twr Address hold from write pulse deassertion
Tas Address setup to write pulse assertion
SROM Initialization B–5