User`s guide

Table B–1 (Cont.) Output Parameter Descriptions
Output Parameter Parameter Description
r20 (a4) - Active
processor mask
The processor mask identifies each processor that is present
on the current system. Each mask bit corresponds to a
processor number associated by the bit number (that is,
bit 0 corresponds to processor 0). A value of 1 in the mask
indicates that the processor is present; a value of 0
indicates that the processor is not present.
To qualify as present, a processor must be:
• Physically present
• Functioning normally
• Capable of sending and receiving interprocessor
interrupt requests
Uniprocessor systems will pass a value of 1 to this register.
r21 (a5) - System context
value
The context value is interpreted in a system-specific manner.
If the system needs to pass more than one system-specific
parameter, it may pass a context value, which is a physical
address pointer to a data structure of many system-specific
values.
B.1.2 Automatic CPU Speed Detection
The AlphaPC64 real-time clock (RTC) detects the speed of the CPU. This
allows a somewhat generic SROM to support AlphaPC64 systems configured
for different CPU speeds. The speed is determined by counting CPU cycles
between RTC interrupts that are set to occur at known time intervals.
B.1.3 CPU Bus Interface Timing
The AlphaPC64 L2 cache timing is based on CPU speed in addition to fixed
delays associated with the L2 cache subsystem. The pertinent L2 cache delays
used in the calculations result from the logic devices used in the L2 cache
subsystem, SRAM specifications, and board etch delays. This data is used to
calculate the appropriate BIU_CTL register setting, which determines the CPU
pin bus timing.
Tables B–2, B–4, and B–5 describe the fixed delays for the AlphaPC64.
Table B–3 provides the SRAM timing specification definitions.
B–4 SROM Initialization