User`s guide

A.2.13 TLB Data Registers 0 Through 7
The TLB data registers contain the CPU page address associated with the PCI
page address in the TLB tag registers. The registers are shown in Figure A–29
and are defined in Table A–23.
Figure A–29 TLB Data Registers 0 Through 7
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
LJ-04206.AI
MBZ
CPU_PAGE<32:13>
MBZ
Table A–23 TLB Data Registers 0 Through 7
Field Name Type Description
<31:21> Reserved MBZ —
<20:1> CPU_PAGE<32:13> RO CPU page. Bits <32:13> of the translated CPU
address can be read or written through this field.
<0> Reserved MBZ —
A.2.14 Translation Buffer Invalidate All Register
The translation buffer invalidate all register (TBIA) is write-only. A write
transaction to this register invalidates all valid entries in the scatter-gather
map TLB.
A–38 System Register Descriptions