User`s guide

A.2.12 TLB Tag Registers 0 Through 7
The TLB tag registers contain the PCI page address associated with the
CPU page address in the TLB data registers. The registers are shown in
Figure A–28 and are defined in Table A–22.
Figure A–28 TLB Tag Registers 0 Through 7
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
LJ-04205.AI
PCI_PAGE<31:13>
EVAL
MBZ
Table A–22 TLB Tag Registers 0 Through 7
Field Name Type Description
<31:13> PCI_PAGE<31:13> RO PCI page. This field specifies the PCI page address
(tag) corresponding to the translated CPU page
address in the associated TLB data register.
<12> EVAL RO Entry valid. The entry valid bit can be read and
written through this bit. Normally, the invalid bit
contains the value read during a page table entry
read transaction.
<11:0> Reserved MBZ —
System Register Descriptions A–37