User`s guide

A.2.11 PCI Master Latency Timer Register
The PCI master latency timer register contains a value that determines
the latency timer period. It should be programmed to be nonzero during
system configuration. The register is shown in Figure A–27 and is defined in
Table A–21.
Figure A–27 PCI Master Latency Timer Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
LJ-04204.AI
MBZ
PMLC<7:0>
Table A–21 PCI Master Latency Timer Register
Field Name Type Description
<31:8> Reserved MBZ —
<7:0> PMLC<7:0> — PCI master latency time. This field is loaded into
the master latency timer register at the start of a
PCI master transaction initiated by the 21071-DA.
The register resets to zero.
A–36 System Register Descriptions