User`s guide

A.2.10 Host Address Extension Register 2
The host address extension register 2 generates ad<31:24> on CPU-initiated
transactions addressing PCI I/O space. It also generates ad<1:0> during
PCI configuration read and write transactions. The register is shown in
Figure A–26 and is defined in Table A–20.
Figure A–26 Host Address Extension Register 2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
LJ-04203.AI
EADDR<7:0>
MBZ
CONF_ADDR<1:0>
Table A–20 Host Address Extension Register 2
Field Name Type Description
<31:24> EADDR<7:0> RW, 0 Extended address. This field is used as the eight
high-order PCI address bits ad<31:24> for CPU-
initiated transactions to PCI I/O space.
<23:2> Reserved MBZ —
<1:0> CONF_ADDR<1:0> RW, 0 Configuration address. This field is used as the
two low-order PCI address bits ad<1:0> for CPU-
initiated transactions to PCI configuration space.
System Register Descriptions A–35