User`s guide

A.2.8 Host Address Extension Register 0
The host address extension register is hardcoded to zero. A read transaction
from this register returns zero; a write transaction has no effect. The register
is shown in Figure A–24.
Figure A–24 Host Address Extension Register 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
LJ-04201.AI
Hardcoded to Zero
A.2.9 Host Address Extension Register 1
The host address extension register 1 generates ad<31:27> on CPU-initiated
transactions addressing PCI memory space. The register is shown in
Figure A–25 and is defined in Table A–19.
Figure A–25 Host Address Extension Register 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
LJ-04202.AI
EADDR<4:0>
MBZ
Table A–19 Host Address Extension Register 1
Field Name Type Description
<31:27> EADDR<4:0> RW, 0 Extension address. This field is used as the five
high-order PCI address bits (ad<31:27>) for CPU-
initiated transactions to PCI memory.
<26:0> Reserved MBZ
A–34 System Register Descriptions