User`s guide

A.2.7 PCI Mask Registers 1 and 2
PCI mask registers 1 and 2 define the size of the target window. The registers
are shown in Figure A–23 and are defined in Table A–18.
Figure A–23 PCI Mask Registers 1 and 2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
LJ-04200.AI
PCI_MASK<31:20>
MBZ
Table A–18 PCI Mask Registers 1 and 2
Field Name Type Description
<31:20> PCI_MASK<31:20> RW PCI mask. This field specifies the size of the PCI
target window; it is also used in the PCI-to-CPU
address translation.
<19:0> Reserved MBZ —
System Register Descriptions A–33