User`s guide

A.2.6 PCI Base Registers 1 and 2

PCI base registers 1 and 2 provide the base address of the target window. The

registers are shown in Figure A–22 and are deﬁned in Table A–17.

Figure A–22 PCI Base Registers 1 and 2

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

LJ-04199.AI

PCI_BASE<31:20>

WENB

SGEN

MBZ

Table A–17 PCI Base Registers 1 and 2

Field Name Type Description

<31:20> PCI_BASE<31:20> RW PCI base. This ﬁeld speciﬁes the base address of the

PCI target window.

<19> WENB RW, 0 Window enable. When this bit is cleared, the PCI

target window is disabled and will not respond to

PCI-initiated transfers. When WENB is set, the

PCI target window is enabled and will respond to

PCI-initiated transfers that hit in the address range

of the target window. This bit should be disabled

by the processor (software) when modifying any of

the PCI target window registers (base, mask, or

translated base).

<18> SGEN RW, 0 Scatter-gather enable. When this bit is cleared, the

PCI target window uses direct mapping to translate

a PCI address to a CPU address. When the bit is set,

the PCI target window uses scatter-gather mapping

to translate a PCI address to a CPU address.

<17:0> Reserved MBZ —

A–32 System Register Descriptions