User`s guide

A.2.5 Translated Base Registers 1 and 2

The translated base registers 1 and 2 provide the base address when mapping

is enabled or disabled. The registers are shown in Figure A–21 and are deﬁned

in Table A–16.

Figure A–21 Translated Base Registers 1 and 2

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

LJ-04198.AI

T_BASE<32:10>

MBZ

Table A–16 Translated Base Registers 1 and 2

Field Name Type Description

<31:9> T_BASE<32:10> RW Translated base. If scatter-gather mapping is disabled,

T_BASE speciﬁes the base CPU address of the

translated PCI address for the PCI target window. If

scatter-gather mapping is enabled, T_BASE speciﬁes

the base CPU address for the scatter-gather map table

for the PCI target window.

<8:0> Reserved MBZ —

System Register Descriptions A–31