User`s guide

A.2.4 PCI Error Address Register
The PCI error address register holds the PCI address ad<31:0> that was being
used when an error happened. The register is shown in Figure A–20 and is
defined in Table A–15.
Figure A–20 PCI Error Address Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
LJ-04197.AI
PCI_ERR<31:0>
Table A–15 PCI Error Address Register
Field Name Type Description
<31:0> PCI_ERR<31:0> RO PCI error. The address sent out on the PCI bus
ad<1:0> as a result of an I/O transaction is stored in
this register. The field logs the address of the errors
indicated by the NDEV, TABT, IOPE, DDPE, IPTL,
and IORT bits in the DCSR. The register is valid
only when one of these error bits is set. If one of the
bits is set, a subsequent error of the same type will
not update the address logged in this register and
the LOST bit is set in DCSR.
A–30 System Register Descriptions