User`s guide

Table A–12 (Cont.) Diagnostic Control and Status Register
Field Name Type Description
<0> TENB RW, 0 TLB enable. When this bit is set, the entire TLB
is enabled. When the bit is cleared, the TLB will
be turned off and subsequent scatter-gather read
transactions will not result in allocation of TLB
entries. Entries that were valid when the TENB bit
was cleared will remain valid. To invalidate entries,
software must write to the TBIA register.
Table A–13 Diagnostic Control and Status Register Field D_BYP<1:0>
Value Mode Description
00 Full bypass PCI-initiated memory read transactions will bypass buffered DMA
write transactions if the double hexword address of the read
transaction does not match that of the buffered write transactions.
The address comparison is done across address bits <31:6>.
01 NA
1
Reserved
10 Partial bypass DMA read transactions will bypass buffered memory write
transactions, if the address within the page does not match that
of the buffered DMA write transactions. The address comparison is
done across bits <12:6>.
11 No bypass DMA read bypassing is disabled. DMA read transactions will be
ordered with respect to DMA write transactions originating on the
PCI.
1
Not applicable
A–28 System Register Descriptions