User`s guide

Table A–12 (Cont.) Diagnostic Control and Status Register
Field Name Type Description
<10> TABT RWC, 0 Target abort. This bit is set when a PCI slave device
ends an I/O read or write transaction using the
PCI target abort protocol. Bits ad<31:0> for this
transaction are logged in the PCI error address
register.
<9> IOPE RWC, 0 I/O parity error. This bit is set when a parity error
occurs in the data phase of an I/O read or write
transaction. Bits ad<31:0> for this transaction are
logged in the PCI error address register.
<8> DDPE RWC, 0 DMA data parity error. This bit is set when a parity
error occurs in the data phase of a DMA transaction.
Bits ad<31:0> for this transaction are logged in the
PCI error address register.
<7> Reserved MBZ —
<6> LOST RWC, 0 Lost error. This bit is set by a 21071-DA error
condition when the address register corresponding to
that error is locked because of a previous error. In
this case, error information for the second error
is lost. The logged address information in the
sysBus error address register or the PCI error
address register will remain valid for the initial
error condition.
<5> IORT RWC, 0 I/O retry timeout. This bit is set when a retry
timeout error occurs on CPU-initiated read or write
transactions on the PCI. Bits ad<31:0> are logged in
the PCI error address register.
<4> DPEC RW, 0 Disable parity error checking. When DPEC is set,
parity checking will not be performed on the PCI bus
(address and data cycles, DMA and I/O transactions).
Parity generation is not affected.
<3> DCEI RW, 0 Disable correctable error interrupt. Not applicable.
Longword parity is implemented on the AlphaPC64.
<2> PENB RWC, 0 Prefetch enable bit. If this bit is set, the sysBus
master state machine will enable prefetching on
DMA read transactions.
<1> Reserved MBZ —
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System Register Descriptions A–27