User`s guide

Table A–12 Diagnostic Control and Status Register
Field Name Type Description
<31> PASS2 RO Pass 2. Chip version reads low on pass 1 and high
on pass 2.
<30:22> Reserved MBZ —
<21:18> PCMD RO PCI command. This field indicates the PCI type
when a PCI-initiated error is logged in the DCSR.
The field is valid only when IPTL, NDEV, TABT, and
IOPE are set.
<17:16> D_BYP<1:0> RW, 0 Disable read bypass. This field is used to control the
order of PCI-initiated memory read transactions with
respect to PCI-initiated memory write transactions.
The three modes are described in Table A–13.
<15> MERR RW, 0 Memory error. This bit is set when the 21071-DA
receives an error code in the iocack<1:0> field in
response to a memory access. Bits sysadr<35:5> for
this transaction are logged in sysBus error address
register bits <31:4>. This bit is not logged if the
sysBus error address register is locked by a previous
error. In this case, the lost error bit is set.
<14> IPTL RWC, 0 Invalidate page table lookup. This bit is set when
the longword scatter-gather map entry being
accessed is invalid. Bits ad<31:0> are logged in
the PCI error address register, if it is not already
locked.
<13> UMRD RWC, 0 Uncorrectable memory read data. This bit is set
when an uncorrectable error is encountered by the
21071-DA in the data read from the DMA read
buffer in the 21071-BA to the 21071-DA on a DMA
read or a scatter-gather read transaction. Bits
sysadr<33:6> for this transaction are logged in
sysBus error address register bits <31:4> if it is not
locked.
<12> CMRD RWC, 0 Correctable memory read data. Not applicable.
Longword parity is implemented on the AlphaPC64.
<11> NDEV RWC, 0 No device. This bit is set when devsel# is not
asserted in response to an I/O read or write
transaction initiated on the PCI by the 21071-DA.
Bits ad<31:0> for this transaction are logged in the
PCI error address register.
(continued on next page)
A–26 System Register Descriptions