User`s guide

Table A–11 (Cont.) Refresh Timing Register

Field Name Type Description

<6:4> REF_RASWIDTH RW, 1 Refresh RAS width. Refresh RAS assertion

width from b<3:0>_ras0_l assertion to

b<3:0>_ras0_l deassertion. b<3:0>_cas0_l

is deasserted with b<3:0>_ras0_l for

refresh. Corresponds to DRAM parameter

RAS

<3:1> REF_CAS2RAS RW, 1 Refresh CAS assertion to RAS assertion

cycles. Corresponds to DRAM parameter

CSR

<0> DISREF RW, 0 Disable refresh. Refresh operations will

not be performed when DISREF is set.

The other timings in this register should

not be changed while this bit is set.

FORCE_REF overrides DISREF.

A.2 DECchip 21071-DA CSR Descriptions

All CSRs are addressed on cache line boundaries (that is, address bits <4:2>

must be zero). Register addresses are speciﬁed in Table 4–3.

Write transactions to read-only registers do not cause errors and are

acknowledged as normal. Only zeros should be written to unspeciﬁed bits

within a register. Registers are initialized as speciﬁed in the register ﬁeld

descriptions.

In the implementation, address bits <27:11> are treated as a don’t care state.

Therefore, accesses to addresses in 21071-DA CSR space with nonzero address

bits <27:11> will map to the corresponding CSR address with address bits

<27:11> equal to zero.

A.2.1 Dummy Registers 1 Through 3

These three registers have no side effects on write transactions and they return

zero on read transactions. Write transactions to these registers can be used

to pack the 21064A write buffers to prevent merging of sparse space I/O write

transactions. Software will not be forced to use an MB instruction between

write transactions if this mechanism is used.

A–24 System Register Descriptions