User`s guide

A.1.8.8 Refresh Timing Register
The refresh timing register contains refresh timing information used to
simultaneously refresh all bank sets using CAS-RAS refresh. Therefore, these
parameters should be programmed to the most conservative values across all
sets.
All the timing parameters are in multiples of memclk cycles. The parameters
have a minimum value that is added to the programmed value. The
programmer should be careful to subtract this minimum value from the desired
value before writing the value to the register.
The refresh timing register is shown in Figure A–17 and is defined in
Table A–11.
Figure A–17 Refresh Timing Register
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
LJ-04194.AI
FORCE_REF
MBZ
REF_INTERVAL
REF_RASWIDTH
REF_CAS2RAS
DISREF
Table A–11 Refresh Timing Register
Field Name Type Description
<15> FORCE_REF RW, 1 Force refresh. Writing a 1 to this bit
causes a single memory refresh. Reads
as 0. Resets the internal refresh interval
counter.
<14:13> Reserved MBZ —
<12:7> REF_INTERVAL RW,
000001
2
Refresh interval. Multiplied by 64 to
generate number of memclk cycles
between refresh requests. A programmed
value of zero is illegal.
(continued on next page)
System Register Descriptions A–23