User`s guide

A.1.8.7 Global Timing Register
The global timing register contains parameters that are common to all memory
bank sets. Each parameter counts memclk cycles. All pins on the memory
interface are referenced to memclk rising. The global timing register is shown
in Figure A–16 and is defined in Table A–10.
Figure A–16 Global Timing Register
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
LJ-04193.AI
MBZ
GTR_MAX_RAS_WIDTH
GTR_RP
Table A–10 Global Timing Register
Field Name Type Description
<15:6> Reserved MBZ —
<5:3> GTR_MAX_RAS_
WIDTH
— Maximum RAS assertion width. Maximum RAS
assertion width as a multiple of 128 memclk
cycles. When this count is reached, the signal
b<3:0>_ras0_l is deasserted at the end of the
ongoing transaction. This value should be
programmed with sufficient margin to allow
for the timer overflowing during a transaction.
Corresponds to DRAM parameter t
RAS
.
When programmed to a 0, page mode between
transactions will be disabled.
<2:0> GTR_RP — Minimum number of RAS precharge cycles.
Cycles extend from b<3:0>_cas0_l deassertion
to next assertion of the same b<3:0>_cas0_l pin.
Corresponds to DRAM parameter t
RP
.
.
A–22 System Register Descriptions