User`s guide

Table A–8 (Cont.) Bank Set Timing Register A
Field Name Type Description
<11:9> S8_RDLYROW RW, 1 Read delay from row address. Delay from row
address to latching first valid read data.
.
<8:7> S8_COLHOLD RW, 1 Column hold. Column hold (t
CAH
) from b0_cas<1:0>_l
assertion. Used to determine when the current
column address can be changed to the next column
or row address.
.
<6:4> S8_COLSETUP RW, 0 Column address setup. Column address setup
(t
ASC
) to first CAS assertion and write enable setup
(t
CWL
) to CAS assertion. Used to determine first
b0_cas<1:0>_l assertion after column address and
b<1:0>_cas<1:0>_l assertion after b0_l<3:0>_we_l.
The maximum of the two setup values should be
programmed. A programmed value of 7 is illegal.
.
<3:2> S8_ROWHOLD — Row address hold. Used to switch memadr from
row to column after b<1:0>_ras_l assertion.
.
<1:0> S8_ROWSETUP RW, 1 Row address setup. Used to generate b<1:0>_ras0_l
assertion from row address.
.
Bank Set Timing Register B
Bank set timing register B is shown in Figure A–15 and is defined in
Table A–9.
System Register Descriptions A–19