User`s guide

On reset, all the parameters are set to the maximum value. This may not
result in correct operation on the memory interface. Therefore, the timing
registers should be programmed by software before setting the corresponding
bank set valid bit in the configuration register.
All the timing parameters are in multiples of memclk cycles. Most of the
timing parameters in timing registers A and B have a minimum value that is
added to the programmed value. The programmer should be careful to subtract
this value from the desired value before programming it into the register.
The description of the parameters also indicates the corresponding DRAM
parameter.
Bank Set Timing Register A
Bank set timing register A is shown in Figure A–14 and is defined in
Table A–8.
Figure A–14 Bank Set Timing Register A
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
LJ-04191.AI
MBZ
S8_RDLYCOL
S8_RDLYROW
S8_COLHOLD
S8_COLSETUP
S8_ROWHOLD
S8_ROWSETUP
Table A–8 Bank Set Timing Register A
Field Name Type Description
<15> Reserved MBZ —
<14:12> S8_RDLYCOL RW, 1 Read delay from column address. Used only when
starting in page mode. Delay from column address
to latching first valid read data.
.
(continued on next page)
A–18 System Register Descriptions