User`s guide

Table A–7 (Cont.) Bank Set 8 Configuration Register
Field Name Type Description
<5> S8_SUBENA RW, 0 Enable subbanks. When set, subbanks are enabled
and determined according to S8_SIZE. When clear,
subbanks are disabled, and the b<1:0>_rasb0_l pins
will be asserted only during refresh.
<4:1> S8_SIZE RW, 0 Bank set 8 size. Indicates the size of the bank set to
determine which bits are used in comparing the base
address with the physical address and for selecting
the subset (if S8_SUBENA is set). Corresponds to
the total size of bank set 8, including subbanks, if
present. The S8_SIZE field codes are listed here:
S8_SIZE
<3:0> Compared Subbank
Bank Set
Size
0XXX — — Reserved
1000 — PA<23> Reserved
1001 PA<33:23> PA<22> 8MB
1010 PA<33:22> PA<21> 4MB
1011 PA<33:21> PA<20> 2MB
1100 PA<33:20> PA<19> 1MB
1101 — — Reserved
1110 — — Reserved
1111 — — Reserved
<0> S8_VALID RW, 0 Register valid bit. If set, all parameters are valid
and access to bank set 8 is allowed. If cleared, no
accesses to bank set 8 are allowed. DMA accesses
to this bank should not be performed when error
checking is disabled.
A.1.8.6 Bank Set Timing Registers A and B
Each bank set has two timing registers (A and B) associated with it. These
registers contain the timing parameters required to perform memory read and
write transactions. The format of the timing registers is identical for all bank
sets.
System Register Descriptions A–17