User`s guide
Table A–6 (Cont.) Bank Set 0 to 7 Configuration Register
Field Name Type Description
<5> S0_SUBENA RW, 0 Enable subbanks. When set, subbanks are enabled
and are determined according to S0_SIZE. When
clear, subbanks are disabled, and the <3:0>_rasb0_l
pins will be asserted only during refreshes.
<4:1> S0_SIZE RW Bank set 8 size in megabytes. Indicates the size
of the bank set to determine which bits are used
in comparing the bank set base address with
the physical address (PA) and for generating the
subset. Corresponds to the total size of the bank set,
including subbanks, if present. S0_SIZE<3> must be
set to 0. S0_SIZE<3:0> field codes are listed here:
S0_SIZE
<3:0> Compared Subset Set Size
0000 — — Reserved
0001 PA<33:29> PA<28> 512MB
0010 PA<33:28> PA<27> 256MB
0011 PA<33:27> PA<26> 128MB
0100 PA<33:26> PA<25> 64MB
0101 PA<33:25> PA<24> 32MB
0110 PA<33:24> PA<23> 16MB
0111 PA<33:23> PA<22> 8MB
1XXX — — Reserved
<0> S0_VALID RW, 0 Bank set 0 valid. If set, all timing and configuration
parameters for bank set 0 are valid, and access to
bank set 0 is allowed. If cleared, access to bank set
0 is not allowed.
Bank Set 8 Configuration Register
Bank set 8 is the VRAM bank; it supports minimum DRAM sizes and
configurations that differ from bank set 0 to 7. The bank set 8 configuration
register is shown in Figure A–13 and is defined in Table A–7.
System Register Descriptions A–15