User`s guide

Bank Set 0 to 7 Conﬁguration Registers

Bank set 0 to 7 conﬁguration registers have the same format and also have the

same limits on bank set size and type of DRAMs used. With the exception of

the valid bit, these registers are not initialized. Bank set 0 to 7 registers are

shown in Figure A–12 and are deﬁned in Table A–6.

Figure A–12 Bank Set 0 to 7 Conﬁguration Register

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

LJ-04189.AI

MBZ

S0_COLSEL

S0_SUBENA

S0_SIZE

S0_VALID

Table A–6 Bank Set 0 to 7 Conﬁguration Register

Field Name Type Description

<15:9> Reserved MBZ —

<8:6> S0_COLSEL RW Column address selection. Indicates the number

of valid column bits expected at the DRAMs. Used

together with memory width information to generate

row or column addresses. Memory interface width

is set at 128 bits. S0_COLSEL<2:0> ﬁeld codes are

listed here:

S0_COLSEL<2:0> Row, Column Bits

000 12, 12

001 12, 10 or 11, 11

010 Reserved

011 10, 10

1XX Reserved

(continued on next page)

A–14 System Register Descriptions