User`s guide

The number of bits that are compared depends on the size of the corresponding
bank set. Bank sets 7 to 0 have an 11-bit field, limiting the minimum DRAM
bank set size to 8MB. Bits <15:5> in the register correspond to sysadr<33:23>.
Bank set 8, which can contain video RAMs and has a minimum size of 1MB,
has the same 11-bit field, where bits <15:5> in the register correspond to
sysadr<33:23> while sysadr<22:20> are compared with zero.
The base address of each bank set must begin on a naturally aligned boundary
(so for a bank set with 2
n
addresses, the n least significant bits must be zero).
Bank set 8 must be placed on an aligned 8MB boundary for bank sizes less
than or equal to 8MB.
If bank set 8 has parity checking disabled (S8_CHECK is clear), then bank set
8 must be mapped into noncacheable space (S8_BASEADR<32> is set).
Register bits <4:0> are reserved and must be zero.
A.1.8.5 Configuration Registers
Each memory bank set has a corresponding configuration register that contains
mode bits, memory address generation bits, and bank set decoding bits. Bank
set 0 to 7 configuration registers differ from the bank set 8 configuration
register.
System Register Descriptions A–13