User`s guide

A.1.8.3 Presence Detect High-Data Register
The presence detect high-data register is shown in Figure A–10. The register
stores the high-order bits of the presence detect data that was shifted in after
reset. Bits <15:0> in the register represent data bits <31:16> that were shifted
in.
Note
After deassertion of reset, it takes 148 system clock cycles for this data
to become valid.
Figure A–10 Presence Detect High-Data Register
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
LJ-04187.AI
PRES_DET<31:16>
A.1.8.4 Base Address Registers
Each memory bank set has a corresponding base address register as shown in
Figure A–11.
Figure A–11 Bank Set 0 Base Address Register
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
LJ-04188.AI
S0_BASEADR<33:23>
MBZ
The bits in this register are compared with the incoming sysBus address
sysadr<33:23> to determine the bank set being addressed. The contents of
this register are validated by setting the valid bit in the configuration register
of that bank set.
A–12 System Register Descriptions