User`s guide

A.1.8 Memory Control Registers
This section describes and defines 21071-CA registers that control memory
configuration and timing. Each bank set of memory has one configuration
register and two timing registers. The global timing register and refresh
timing register apply to all bank sets. The video frame pointer is used for
video transactions to bank set 8.
A.1.8.1 Video Frame Pointer Register
The video frame pointer register is shown in Figure A–8 and is defined in
Table A–5. The register contains address information that points to the
beginning of the video frame buffer. The video frame pointer is loaded into
the video display pointer at the beginning of each full serial transfer to bank
set 8. This register is not initialized.
Figure A–8 Video Frame Pointer Register
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
LJ-04185.AI
MBZ
VFP_SUBBANK
VFP_ROWADR
VFP_COLADR
Table A–5 Video Frame Pointer Register
Field Name Type Description
<15> Reserved MBZ —
<14> VFP_SUBBANK RW Video frame subbank pointer. Subbank for the start
of the frame buffer. If the subbank is enabled by
setting S8_SUBENA in the bank set 8 configuration
register, setting the VFP_SUBBANK bit causes
the 21071-CA to assert v<1:0>_rasb8_l instead
of v<1:0>_ras8_l on full serial register loads.
VFP_SUBBANK is ignored if S8_SUBENA is
cleared.
<13:5> VFP_ROWADR RW Video frame row address pointer. Row address of the
start of the frame buffer.
(continued on next page)
A–10 System Register Descriptions