User`s guide

Table A–4 (Cont.) Maximum Memory Tag Enable Values
TAGEN<15:0>
Compared
Bits Memory Size
0000 0011 1111 1110 <25:17> 64MB
0000 0001 1111 1110 <24:17> 32MB
0000 0000 1111 1110 <23:17> 16MB
0000 0000 0111 1110 <22:17> 8MB
0000 0000 0011 1110 <21:17> 4MB
0000 0000 0000 1110 <19:17> 1MB
0000 0000 0000 0110 <18:17> 512KB
0000 0000 0000 0010 <17> 256KB
0000 0000 0000 0000 None 128KB
A.1.4 Error Low Address Register
The error low address register is shown in Figure A–4. The register locks the
low order bits of the sysBus address (sysadr<20:5>) that caused the error
and set the BC_TAPERR, BC_TCPERR, or NXMERR bit in the error and
diagnostic status register. If a victim read caused the error, the victim address
is not latched; rather, the address of the transaction is latched. Bits <15:0>
represent sysadr<20:5>. This register is read-only. It is not initialized and is
valid only when an error is indicated.
Figure A–4 Error Low Address Register
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
LJ-04181.AI
ERR_LADR<20:5>
A.1.5 Error High Address Register
The error high address register is shown in Figure A–5. The register locks
the high order bits of the sysBus address (sysadr<33:21>) that caused the
error. Bits <12:0> represent sysadr<33:21>. This register is read-only. It is
not initialized and is only valid when an error is indicated. Bits <15:13> are
reserved and must be zero.
A–8 System Register Descriptions