User`s guide

A.1.3 Tag Enable Register
The tag enable register, shown in Figure A–3, indicates which bits of the cache
tag are to be compared with sysadr<33:5>. If a bit is 1, the corresponding
bits in sysadr<33:5> and systag<31:17> are compared. If a bit is 0, there
is no comparison for those bits, and the systag bit is assumed to be tied low
on the module (through a resistor). Bits <15:1> in the register represent
systag<31:17>. This register is not initialized.
Figure A–3 Tag Enable Register
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
LJ-04180.AI
TAGEN<31:17>
MBZ
There is no requirement that the upper bits of TAGEN<31:17> be set. An
implementation that does not allow the full 4GB cacheable memory to be
installed may choose to mask off upper bits of TAGEN<31:17> and save having
to store a bit of the tag address in the tag address RAM.
To construct TAGEN<31:17>, refer to Tables A–3 and A–4. The value shown
in Table A–3 (based on the cache size) is ANDed with the value in Table A–4
(based on the maximum cacheable system memory). For example, a system
with a 16MB cache, and a maximum of 1GB cacheable memory would program:
1111 1111 0000 000X ANDed with
0011 1111 1111 111X gives
0011 1111 0000 000X which is put into TAGEN.
A–6 System Register Descriptions