User`s guide

Table A–2 (Cont.) Error and Diagnostic Status Register
Field Name Type Description
<13> PASS 2 RO Chip version reads low on pass 1 and high on
pass 2.
<12:9> Reserved MBZ —
<8:6> CREQCAUSE RO Cycle request that caused error. Indicates
the DMA or CPU cycle request type that
caused the error. Contains a copy of either
the cpucreq or iocmd signal lines, depending
on DMACAUSE<4>. Locked with the error
address. Only valid when an error is indicated
on BC_TAPERR, BC_TCPERR, or MEMERR.
<5> VICCAUSE RO Victim write caused error. When set, indicates
that an NXM error was caused by a victim write
transaction. Undefined for other types of errors.
Locked with the error address. Valid only when an
error is indicated on BC_TAPERR, BC_TCPERR,
or MEMERR.
<4> DMACAUSE RO DMA transaction caused error. When set, indicates
that the BC_TAPERR, BC_TCPERR, or NXMERR
was caused by a DMA transaction. Locked with
the error address. Valid only when an error
is indicated on BC_TAPERR, BC_TCPERR, or
MEMERR.
<3> NXMERR RW1C, 0 Nonexistent memory error. When set, indicates
that a read or write transaction occurred to
an invalid address that does not map to any
memory bank, CSR, or I/O quadrant. Set only
when address is unlocked.
<2> BC_TCPERR RW1C, 0 L2 cache tag control parity. When set, indicates
that a tag probe encountered bad parity in the tag
control RAM. Set only when address is unlocked.
<1> BC_TAPERR RW1C, 0 L2 cache tag address parity. When set, indicates
that a tag probe encountered bad parity in the tag
address RAM. Set only when address is unlocked.
<0> LOSTERR RW1C, 0 Lost error, multiple errors. When set, indicates
that additional errors occurred after an error
address was locked. No address or cause
information is latched for the error.
System Register Descriptions A–5