User`s guide

Table A–1 (Cont.) General Control Register
Field Name Type Description
<9> BC_FRCTAG RW, 0 L2 cache force tag. When set, the LE cache will be
probed for victims, and the line will be invalidated
using the values in the BC_FRCD, BC_FRCV, and
BC_FRCP fields. CSRs will be used as the tag
controls. Although the line is invalidated (assuming
BC_FRCV is reset), the data is loaded into the cache,
and will be returned to the CPU as cacheable.
Used for diagnostic testing of the cache RAM and
for flushing the cache by setting this bit, clearing
BC_FRCV, and cycling through the address range
present in the cache.
<8> BC_IGNTAG RW, 0 L2 cache ignore tag. When set, L2 cache probes will
act as if the valid bit was invalid. All tag results will
be ignored (and any victims will be lost). Tag and
address parity will be ignored. This field may be used
to fill the cache with valid data.
<7> BC_LONGWR RW, 0 L2 cache long write transactions. When set, two
sysBus cycles are required to write to the cache data
RAMs.
<6> BC_NOALLOC RW, 0 L2 cache no allocate mode. When set, CPU write
transactions to cacheable memory space will not be
allocated into the cache.
<5> BC_EN RW, 0 L2 cache enable. When clear, the L2 cache is disabled
and the cache state machine will not probe the cache.
<4> WIDEMEM RO Wide memory size. Reads the status of the widemem
input pin. Returns 1 for the 128-bit memory interface.
<3> Reserved MBZ —
<2:1> SYSARB RW, 0 DMA arbitration mode. Determines arbitration
scheme for sysBus transactions.
Value Meaning
0X CPU priority
10 DMA priority
11 DMA strong priority
<0> Reserved MBZ —
System Register Descriptions A–3