User`s guide

Figure A–1 General Control Register
15
MBZ
14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
LJ-04178.AI
MBZ
BC_BADAP
BC_FRCP
BC_FRCV
BC_FRCD
BC_FRCTAG
BC_IGNTAG
BC_LONGWR
BC_NOALLOC
BC_EN
WIDEMEM
MBZ
SYSARB
MBZ
Table A–1 General Control Register
Field Name Type Description
<15:14> Reserved MBZ —
<13> BC_BADAP RW, 0
1
L2 cache force bad address parity. When set, the tag
address parity will be loaded as bad (independent of
the BC_FRCTAG bit).
<12> BC_FRCP RW, 0 L2 cache force parity. When set, the parity bit will be
set on the next cache fill.
<11> BC_FRCV RW, 0 L2 cache force valid. When set, the valid bit will be
set on the next cache fill.
<10> BC_FRCD RW, 0 L2 cache force dirty. When set, the dirty bit will be set
on the next cache fill.
1
Register field content after reset
(continued on next page)
A–2 System Register Descriptions