User`s guide

A
System Register Descriptions
This appendix describes the control and status registers (CSRs) of the
DECchip 21071-CA (Sections A.1 and A.1.8) and DECchip 21071-DA
(Section A.2).
A.1 DECchip 21071-CA CSR Descriptions
The CSRs are 16 bits wide and are addressed on cache-line boundaries.
Write transactions to read-only registers could result in UNPREDICTABLE
behavior; read transactions are nondestructive. Only zeros should be written
to unspecified bits within a CSR. Only bits <15:0> of each register are defined.
Other bits are undefined. CSRs are initialized as shown in the type field of
register descriptions.
Register addresses are specified in Table 4–2.
A.1.1 General Control Register
The general control register is shown in Figure A–1 and is defined in
Table A–1. The register contains status information that affects the major
operational modes of the 21071-CA.
System Register Descriptions A–1