User`s guide

A–9 Bank Set Timing Register B ......................... A–21
A–10 Global Timing Register . . ........................... A–22
A–11 Refresh Timing Register . ........................... A–23
A–12 Diagnostic Control and Status Register ................. A–26
A–13 Diagnostic Control and Status Register Field
D_BYP<1:0> ..................................... A–28
A–14 sysBus Error Address Register ....................... A–29
A–15 PCI Error Address Register .......................... A–30
A–16 Translated Base Registers 1 and 2 . . ................... A–31
A–17 PCI Base Registers 1 and 2 .......................... A–32
A–18 PCI Mask Registers 1 and 2 ......................... A–33
A–19 Host Address Extension Register 1 . ................... A–34
A–20 Host Address Extension Register 2 . ................... A–35
A–21 PCI Master Latency Timer Register. ................... A–36
A–22 TLB Tag Registers 0 Through 7 ....................... A–37
A–23 TLB Data Registers 0 Through 7 . . . ................... A–38
B–1 Output Parameter Descriptions ....................... B–2
B–2 Cache Loop Delay Characteristics . . ................... B–5
B–3 SRAM Timing Specification Definitions ................. B–5
B–4 Worst-Case SRAM Timing Specifications ................ B–6
B–5 CPU Specifications ................................. B–6
B–6 Special Header Entry Descriptions . ................... B–11
B–7 Higher 512KB Flash ROM Image Selection .............. B–13
B–8 Jumper Position Descriptions (Repeated) ............... B–17
C–1 SIO PCI-to-ISA Bridge Operating Register Address Space
Map............................................ C–1
C–2 Address Bits and PCI Device idsel Pins ................. C–5
C–3 SIO PCI-to-ISA Bridge Configuration Address Space Map . . . C–6
C–4 PC87312 Combination Controller Register Address Space
Map............................................ C–8
C–5 Integrated Device Electronics (IDE) Register Addresses . . . . C–10
C–6 Utility Bus Device Decode ........................... C–11
C–7 Interrupt Control PLD Addresses . . ................... C–12
C–8 Keyboard and Mouse Controller Addresses .............. C–12
C–9 Time-of-Year Clock Device Addresses ................... C–13
C–10 Flash Memory Segment Select Register ................. C–14
C–11 Flash Memory Addresses (Within Segment).............. C–14
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