User`s guide

Each SG map entry maps an 8KB page of PCI address space into an 8KB page
of processor address space. Each SG map entry is a quadword. Each entry has
a valid bit in position 0. Address bit ad<13> is at bit position 1 of the map
entry. Because the 21072 implements only valid memory addresses up to 6GB,
bits ad<63:21> of the SG map entry must be programmed to 0. Bits ad<21:1>
of the SG entry generate the physical page address. This is appended to bits
ad<12:5> of the incoming PCI address to generate the memory address placed
on the sysBus. Figure 4–5 shows the SG map entry.
Figure 4–5 SG Map Page Table Entry in Memory
LJ03956A.AI
63 32
MBZ
31 20 000121
Page Address <32:13> ValidMBZ
The size of the SG map table is determined by the size of the PCI target
window as defined by the PCI mask register (see Table 4–10). Because the
SG map is located in system memory, sysBus<33> is always zero. Bits
sysBus<32:2> are obtained from the translated base register and the PCI
address.
System Address Mapping 4–23