User`s guide

Tables
1 Register Field Type Notation . ........................ xvi
2 Unnamed Register Field Notation ..................... xvii
3 Data Units ....................................... xvii
4 Signal References . . ................................ xviii
1–1 L2 Cache SIMM Sizes .............................. 1–4
2–1 Jumper Position Descriptions. ........................ 2–3
2–2 AlphaPC64 Board Jumpers . . ........................ 2–5
2–3 Module Connector Descriptions ....................... 2–8
3–1 TriQuint Operating Frequencies ...................... 3–24
3–2 Clock Divisor Range (21064A)........................ 3–25
3–3 Distribution of 66-MHz Clock Signals . . ................ 3–28
3–4 Distribution of 33-MHz Shifted Clock Signals ............ 3–28
3–5 Distribution of 33-MHz Clock Signals . . ................ 3–29
3–6 CPU Interrupt Assignment . . ........................ 3–30
4–1 sysBus Address Space Description..................... 4–3
4–2 DECchip 21071-CA CSR Register Addresses ............. 4–5
4–3 DECchip 21071-DA CSR Register Addresses ............. 4–7
4–4 PCI Sparse I/O Space Byte Enable Generation ........... 4–11
4–5 PCI Configuration Space Definition .................... 4–12
4–6 PCI Address Decoding for Primary Bus Configuration
Accesses . ........................................ 4–13
4–7 PCI Sparse Memory Space Byte Enable Generation ....... 4–17
4–8 PCI Target Window Enables . ........................ 4–20
4–9 PCI Target Address Translation—Direct Mapped . . ....... 4–22
4–10 Scatter-Gather Map Address . ........................ 4–24
5–1 Power Supply dc Current Requirements (275 MHz). ....... 5–1
5–2 Major Board Component Descriptions . . ................ 5–4
A–1 General Control Register ............................ A–2
A–2 Error and Diagnostic Status Register . . ................ A–4
A–3 Cache Size Tag Enable Values ........................ A–7
A–4 Maximum Memory Tag Enable Values . . ................ A–7
A–5 Video Frame Pointer Register ........................ A–10
A–6 Bank Set 0 to 7 Configuration Register . ................ A–14
A–7 Bank Set 8 Configuration Register..................... A–16
A–8 Bank Set Timing Register A . ........................ A–18
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