AlphaPC64 Evaluation Board User’s Guide Order Number: EC–QGY2C–TE Revision/Update Information: Digital Equipment Corporation Maynard, Massachusetts This document supersedes the AlphaPC64 Evaluation Board User’s Guide (EC–QGY2B–TE).
July 1995 While Digital believes the information included in this document is correct as of the date of publication, it is subject to change without notice. Digital Equipment Corporation makes no representations that the use of its products in the manner described in this publication will not infringe on existing or future patent rights, nor do the descriptions contained in this publication imply granting of licenses to make, use, or sell equipment or software in accordance with the description.
Contents Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii 1 AlphaPC64 Introduction 1.1 1.1.1 1.1.2 1.1.3 1.1.4 1.1.5 1.1.6 1.1.7 1.1.8 1.1.9 1.2 System Components and Features . . . . . Memory Subsystem . . . . . . . . . . . . . DECchip 21072 Support Chipset . . . PAL Control Set . . . . . . . . . . . . . . . . Level 2 Cache Subsystem Overview . Clock Subsystem Overview . . . . . . . PCI Interface Overview . . . . . . . . . .
3.2.1 sysBus Interface . . . . . . . . . . . . . . . . . . . . . . . 3.2.1.1 sysBus Arbitration . . . . . . . . . . . . . . . . . . 3.2.1.2 L2 Cache Control . . . . . . . . . . . . . . . . . . . 3.2.1.3 sysBus Control . . . . . . . . . . . . . . . . . . . . . 3.2.1.4 Address Decoding . . . . . . . . . . . . . . . . . . . 3.2.1.5 Error Handling . . . . . . . . . . . . . . . . . . . . 3.2.2 Memory Controller . . . . . . . . . . . . . . . . . . . . . 3.2.2.1 Memory Organization . . . . . . . . . . . . . . . 3.
3.4.7 3.4.8 3.4.9 3.4.10 3.4.11 3.5 3.6 3.6.1 3.6.2 3.7 3.7.1 3.7.2 3.8 3.8.1 3.8.2 3.8.3 3.9 3.9.1 3.9.2 3.9.3 3.9.4 3.9.5 3.10 3.11 3.12 3.13 3.13.1 3.13.2 3.13.3 DMA Write Buffer . . . . . . . . . . . Memory Write Buffer . . . . . . . . . Error Checking . . . . . . . . . . . . . epiBus Data Path . . . . . . . . . . . . sysBus Output Selectors . . . . . . Error Handling . . . . . . . . . . . . . . . . Clock Subsystem . . . . . . . . . . . . . . . TriQuint PLL Clock Oscillator . .
4.1.7 4.1.7.1 4.1.7.2 4.1.8 4.1.9 4.2 PCI Configuration Space (1 E000 0000 to 1 FFFF FFFF) . PCI Configuration Cycles to Primary Bus Targets . . . . PCI Configuration Cycles to Secondary Bus Targets . . PCI Sparse Memory Space (2 0000 0000 to 2 FFFF FFFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Dense Memory Space (3 0000 0000 to 3 FFFF FFFF) . PCI-to-Physical Memory Addressing . . . . . . . . . . . . . . . . . . . . .. .. .. 4–12 4–14 4–14 .. .. ..
A.2.10 A.2.11 A.2.12 A.2.13 A.2.14 Host Address Extension Register 2 . . . . . PCI Master Latency Timer Register . . . . . TLB Tag Registers 0 Through 7 . . . . . . . . TLB Data Registers 0 Through 7 . . . . . . . Translation Buffer Invalidate All Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–35 A–36 A–37 A–38 A–38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D Technical Support and Ordering Information D.1 D.2 D.3 D.4 D.5 Technical Support . . . . . . . . . . . . . . . . . . . . Ordering Alpha Microprocessor Sample Kits Ordering Digital Semiconductor Products . . Ordering Associated Literature . . . . . . . . . . Ordering Third-Party Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–5 4–6 5–1 A–1 A–2 A–3 A–4 A–5 A–6 A–7 A–8 A–9 A–10 A–11 A–12 A–13 A–14 A–15 A–16 A–17 A–18 A–19 A–20 A–21 A–22 A–23 A–24 A–25 A–26 A–27 A–28 A–29 B–1 B–2 B–3 SG Map Page Table Entry in Memory . . . . . . . SG Map Translation of PCI to SysBus Address Major Board Component Layout . . . . . . . . . . . General Control Register . . . . . . . . . . . . . . . . . Error and Diagnostic Status Register . . . . . . . Tag Enable Register . . . . . . . . . . . . . . . . . . . . . Error Low Address Register . . . . .
Tables 1 2 3 4 1–1 2–1 2–2 2–3 3–1 3–2 3–3 3–4 3–5 3–6 4–1 4–2 4–3 4–4 4–5 4–6 4–7 4–8 4–9 4–10 5–1 5–2 A–1 A–2 A–3 A–4 A–5 A–6 A–7 A–8 x Register Field Type Notation . . . . . . . . . . . . . . . . . . . . Unnamed Register Field Notation . . . . . . . . . . . . . . . . Data Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . L2 Cache SIMM Sizes . . . . . . . . . . . . . . . . . . . . . . . . .
A–9 A–10 A–11 A–12 A–13 A–14 A–15 A–16 A–17 A–18 A–19 A–20 A–21 A–22 A–23 B–1 B–2 B–3 B–4 B–5 B–6 B–7 B–8 C–1 C–2 C–3 C–4 C–5 C–6 C–7 C–8 C–9 C–10 C–11 Bank Set Timing Register B . . . . . . . . . . . . . . . . . . . . . . . Global Timing Register . . . . . . . . . . . . . . . . . . . . . . . . . . . Refresh Timing Register . . . . . . . . . . . . . . . . . . . . . . . . . . Diagnostic Control and Status Register . . . . . . . . . . . . . . . Diagnostic Control and Status Register Field D_BYP<1:0> . . . .
C–12 C–13 xii Flash ROM Configuration Registers . . . . . . . . . . . . . . . . . . . . Memory Map of Flash Memory . . . . . . . . . . . . . . . . . . . . . . .
Preface This guide describes the AlphaPC64 Evaluation Board. The board is an evaluation and development module for computing systems based on the Alpha 21064A microprocessor. Audience This guide is written for system designers and others who use the AlphaPC64 to design or evaluate computer systems based on the Alpha 21064A microprocessor. Scope This guide describes the features, configuration, functional operation, and interfaces of the AlphaPC64.
• Chapter 5, Board Requirements and Parameters, describes the board power and environmental requirements, and identifies major board components. • Appendix A, System Register Descriptions, describes the control and status registers of the DECchip 21071-CA and DECchip 21071-DA. • Appendix B, SROM Initialization, describes the general SROM, Level 2 (L2) cache, and memory initialization steps and associated parameters.
Ranges and Extents Ranges are specified by a pair of numbers separated by two periods (..) and are inclusive. For example, a range of integers 0..4 includes the integers 0, 1, 2, 3, and 4. Extents are specified by a pair of numbers in angle brackets (<>) separated by a colon ( : ) and are inclusive. For example, bits <7:3> specifies an extent including bits 7, 6, 5, 4, and 3.
Register Field Notation Register figures and tabulated descriptions have a mnemonic that indicates the bit or field as described in Table 1. Table 1 Register Field Type Notation xvi Notation Description RW A read/write bit or field. The value may be read and written by software, microcode, or hardware. RO A read-only bit or field. The value may be read by software, microcode, or hardware. It is written by hardware; software or microcode write transactions are ignored. WO A write-only bit or field.
Other register fields that are unnamed may be labeled as specified in Table 2. Table 2 Unnamed Register Field Notation Notation Description 0 A 0 in a bit position indicates a register bit that is read as a 0 and is ignored on a write transaction. 1 A 1 in a bit position indicates a register bit that is read as a 1 and is ignored on a write transaction. x An x in a bit position indicates a register bit that does not exist in hardware.
Schematic References Logic schematics are included in the AlphaPC64 design package. In this guide, references to schematic pages are printed in italics. For example, the following specifies schematic page 3: ‘‘. . . the 300-MHz oscillator (AlphaPC64.3) supplies . . .’’ In some cases, more than one schematic page is referenced. For example, the following specifies schematic pages 17 through 20: ‘‘. . . the DRAM buffers (AlphaPC64.17–20) . . .
1 AlphaPC64 Introduction The AlphaPC64 Evaluation Board (AlphaPC64) is an evaluation and development module for computing systems based on the Alpha 21064A microprocessor. The AlphaPC64 provides a single-board hardware and software development platform for the design, integration, and analysis of supporting logic and subsystems. The board also provides a platform for peripheral component interconnect (PCI) I/O device hardware and software development.
1.1.1 Memory Subsystem The DRAM memory can provide 16MB to 512MB with a 128-bit data bus. The memory is contained in two banks of four commodity single inline memory modules (SIMMs). Each SIMM is 36 bits wide, with 32 data bits, 1 parity bit, and 3 unused bits with 70-ns or less access. The following SIMM sizes are supported: 1M x 36 2M x 36 4M x 36 8M x 36 16M x 36 1.1.2 DECchip 21072 Support Chipset The 21064A is supported by a DECchip 21072 ASIC chipset (21072), with a 128-bit memory interface.
Figure 1–1 AlphaPC64 Functional Block Diagram 21064A Support L2 Cache Interface - L2 Cache PALs - TriQuint PLL Clock - External Clock Oscillator - Serial Boot ROM - Power Supply - Supervisor - System Clocking L2 Cache Control L2 Cache SIMMs buff_ address - Address Buffers Alpha 21064A Microprocessor Address Running at 200 MHz to 275 MHz - 512KB oe and we - 2MB - 8MB tag_adr - Longword Parity data<127:0> 21072 Chipset Check Bits<21, 14, 7, 0> Address data<15:0> PCI Devices * PCI Bus DECchip
1.1.4 Level 2 Cache Subsystem Overview The external Level 2 (L2) cache subsystem supports 512KB, 1MB, 2MB, 4MB, or 8MB cache sizes by using a 128-bit data bus. The L2 cache size can be reconfigured through onboard hardware and software jumpers. The AlphaPC64 supports the L2 cache SIMM sizes shown in Table 1–1. Two SIMMs are required per system. The AlphaPC64 comes with a 2MB, 12-ns L2 cache.
• Time-of-year (TOY) function provided by a Dallas DS1287 chip • 1MB flash ROM memory using the Intel 28F008SA chip The ISA has two dedicated expansion slots and one shared expansion slot with the PCI. 1.1.8 Software Support Software support includes an industry-standard, 1MB flash ROM containing debug monitor code and a console interface. Source code listings for all software (including boot code and diagnostic ROM monitor) are provided.
1.1.9 Design Support The full database, including schematics and source files, is supplied. User documentation is also included. The database allows designers with no previous Alpha architecture experience to successfully develop a working Alpha system with minimal help. 1.
33.0 cm (13.0 in ± 0.0005 in) Figure 1–2 AlphaPC64 Component Layout and Board Dimensions 22.1 cm (8.7 in ± 0.0005 in) Scale = 90% LJ-04458.
2 System Jumpers and Connectors The AlphaPC64 uses jumpers to implement variations in clock frequency and L2 cache size and speed. These jumpers must be configured for the user’s environment. Onboard connectors are provided for the I/O, memory SIMMs, serial and parallel peripherals, integrated device electronics (IDE) devices, and L2 cache SIMMs. After the module is configured, you can apply power and run the debug monitor.
Figure 2–1 AlphaPC64 Board Jumpers J16 J15 J3 Scale = 90% 2–2 System Jumpers and Connectors LJ-04459.
Figure 2–2 J3 Connector sysclkdiv 1 2 jmp_irq2 3 4 jmp_irq1 5 6 jmp_irq0 7 8 toy_clr 9 10 sp_bit0 11 12 sp_bit1 13 14 sp_bit2 15 16 sp_bit3 17 18 sp_bit4 19 20 sp_bit5 21 22 sp_bit6 23 24 sp_bit7 25 26 gnd reset button 27 28 hd_act_l 29 30 hd_led_l 31 32 gnd spkr 33 34 key_lock vdd 35 36 gnd 37 38 gnd vdd 39 40 power_led_l To Speaker LJ-04132.
Table 2–1 (Cont.) Jumper Position Descriptions Select Bit Register Bit Name Function sp_bit<5:3> BC_SPEED<2:0> L2 cache speed selection is shown here.
2.1.2 Hardware Configuration Jumpers Hardware configuration jumpers are shown in Figure 2–1 and are described in Table 2–2. Table 2–2 AlphaPC64 Board Jumpers Connector Pins Description Note: All other combinations are reserved. L2 Cache Address Lines J15 4 Adr<22:19> L2 cache (AlphaPC64.
Table 2–2 (Cont.) AlphaPC64 Board Jumpers Connector Pins Description System Clock Functions J3 4 21064A CPU clock divisor selection (AlphaPC64.
Figure 2–3 AlphaPC64 Board Connectors J32 J33 J34 J31 J30 J28 J25 J27 J24 J29 J26 J17 J18 J19 J20 J21 J22 J23 J14 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J2 J1 Scale = 90% LJ-04457.
Table 2–3 Module Connector Descriptions Connector Pins Description PCI Connectors J23 124 PCI expansion connector 3 (AlphaPC64.24) J22 124 PCI expansion connector 2 (AlphaPC64.24) J21 124 PCI expansion connector 1 (AlphaPC64.25) J20 124 PCI expansion connector 0 (AlphaPC64.25) ISA Connectors J19 98 ISA expansion connector 2 (AlphaPC64.27) J18 98 ISA expansion connector 1 (AlphaPC64.27) J17 98 ISA expansion connector 0 (AlphaPC64.
Table 2–3 (Cont.) Module Connector Descriptions Connector Pins Description Memory SIMMs J11 72 Bank 0, DRAM 0 SIMM (AlphaPC64.16) J10 72 Bank 0, DRAM 1 SIMM (AlphaPC64.16) J9 72 Bank 0, DRAM 2 SIMM (AlphaPC64.17) J8 72 Bank 0, DRAM 3 SIMM (AlphaPC64.17) J7 72 Bank 1, DRAM 0 SIMM (AlphaPC64.18) J6 72 Bank 1, DRAM 1 SIMM (AlphaPC64.18) J5 72 Bank 1, DRAM 2 SIMM (AlphaPC64.19) J4 72 Bank 1, DRAM 3 SIMM (AlphaPC64.19) J2 6 SROM test data serial port input connector (AlphaPC64.
Table 2–3 (Cont.) Module Connector Descriptions Connector Pins Description J29 6 Module power connector (GND, –5 V, +5 V (Vdd)) (AlphaPC64.38) J31 6 Module power connector (GND, +12 V, –12 V, +5 V (Vdd), p_dcok) (AlphaPC64.38) J28 6 Module power connector (+3.3 V, GND) (AlphaPC64.38) J27 6 Power Connectors Module power connector (GND, +3.3 V) (AlphaPC64.38) Note: Power for the AlphaPC64 is provided by a usersupplied, standard PC power supply which includes 3.3 V dc.
3 Functional Description This chapter describes the functional operation of the AlphaPC64. The description introduces the ASIC support chipset and describes its implementation with the 21064A microprocessor and its supporting memory and I/O devices. Information, such as bus timing and protocol, found in other specifications, data sheets, and reference documentation is not duplicated. Appendix D provides a list of supporting documents and order numbers.
3.1.1 21071-CA Introduction The 21071-CA chip provides the interface between the 21064A and main memory. It provides the system interface to the cache. The chip controls and moves data to and from banks of main memory. It responds to commands from the CPU and 21071-DA and arbitrates between them. It also supports control of the L2 cache RAMs during a CPU cache miss and direct memory access (DMA) transactions. On the AlphaPC64, the 21071-CA controls two banks of DRAM SIMMs.
Figure 3–1 Maximum and Minimum SIMM Bank Layouts Maximum 512MB DRAM Layout - Populated with 16M x 36 SIMMs DRAM 2 - 64MB SIMM memData64 - 95 + Parity J9 DRAM 3 - 64MB SIMM memData96 - 127 + Parity J8 DRAM 0 - 64MB SIMM memData0 - 31 + Parity J11 DRAM 1 - 64MB SIMM memData32 - 63 + Parity J10 Bank 0 256MB 512MB DRAM 2 - 64MB SIMM memData64 - 95 + Parity J5 DRAM 0 - 64MB SIMM memData0 - 31 + Parity J7 Bank 1 256MB DRAM 3 - 64MB SIMM memData96 - 127 + Parity J4 DRAM 1 - 64MB SIMM memData32 - 63
Figure 3–2 Basic Cache and Memory Subsystem Address and Data Paths Tag Adr Ctrl L2 Cache Ctrl SysAdr CPU 21071-CA Memory Address and Control Cache Memory DRAMs sysData <127:0> Check <21, 14, 7, 0> 32 Bits 32 Bits 21071-BA0 21071-BA1 32 Bits 32 Bits 32 Bits 21071-BA2 32 Bits 32 Bits 21071-BA3 32 Bits memData <127:0> memPar <3:0> 21071-DA Data Path Bit Assignments sysData Lines memData Lines 21071-BA0 <31:0> 21071-BA1 <63:32> 21071-BA2 <95:64> 21071-BA3 <127:96> memData <31:0> memData <63:32> me
The 21071-DA provides all controls and interfaces to the PCI and sysBus and contains the following components and functions: • sysBus interface state machine • sysBus address decoder and translator • epiBus arbitration and control • PCI interface, state machines, and parity generation • PCI address decoder and translator Figure 3–3 Basic I/O Subsystem Address and Data Paths sysData <127:0> Check <21,14,7,0> 32 Bits CPU 21071-BA0 32 Bits 32 Bits 21071-BA1 32 Bits 21071-BA2 32 Bits 32 Bits 3
The following list summarizes the major features of the 21071-DA: • Scatter-gather mapping from the 32-bit PCI address to the 34-bit physical address, with an onchip, 8-entry translation lookaside buffer (TLB) for fast address translations. To reduce cost, the scatter-gather tables are stored in memory and are automatically read by the 21071-DA when a translation misses in the TLB. • Supports a maximum PCI burst length of 16 longwords on PCI memory read and write transactions.
3.1.3 21071-BA Introduction The 21071-BA chip provides a 32-bit data path from the 21064A to main memory and I/O. Four chips are required for the 128-bit interface. The chip contains the cache and memory interface data path, which includes buffers for victim, noncacheable write, and DMA write operations. It also contains the I/O subsystem data path, which provides buffering for DMA read and write data, and I/O read and write data. The chip interfaces to the cache and CPU by using the CPU sysBus (pin bus).
3.2 21071-CA Functional Overview The 21071-CA (AlphaPC64.6) provides second-level cache and memory control functions. It also controls the cache and memory data path located on the 21071-BA. Figure 3–4 shows a block diagram of the 21071-CA. Figure 3–4 21071-CA Block Diagram tagadr<31:17> adr<33:5> Tag Compare Address Generation Write Address Write Buffer Address Read Address AlphaPC64.6 Row and Column Generation b0<3:0>_adr<11:0> 48 AlphaPC64.12-14 AlphaPC64.
3.2.1.1 sysBus Arbitration The 21071-CA arbitrates between the CPU and 21071-DA, which requests use of the sysBus and the L2 cache when they have a transaction to perform. The CPU has default ownership of the sysBus so that it can access the L2 cache whenever the 21071-DA is not requesting the bus. 3.2.1.2 L2 Cache Control Figure 3–5 shows the implementation of a cache subsystem with an 8MB cache. Note that the 21071-CA supports a 128-bit secondary cache interface.
3.2.1.3 sysBus Control The sysBus controller consists of a sequencer that receives CPU and DMA command fields for decode, results from the sysBus arbiter logic, and status from the memory controller logic. The sequencer supplies machine state signals that are used to generate L2 cache control and read requests to the memory controller; to load data from the sysBus into the read, merge, and write buffers; and to acknowledge cycles to the CPU and 21071-DA.
3.2.2 Memory Controller This section summarizes memory organization and memory controller features. 3.2.2.1 Memory Organization The 21071-CA supports up to: • Eight bank sets of DRAM (bank sets 0..7), where one bank set equals four SIMMs • One bank set (bank set 8) of VRAM Each bank set can be made up of one or two banks. A bank of memory refers to one width of DRAMs, implemented with SIMMs. The SIMM implementation requires more than one SIMM to form one memory bank.
3.2.2.5 Transaction Scheduler The memory interface does memory refresh, cache-line read and write transactions, and shift register loads to VRAM bank set 8. The memory controller has a scheduler that prioritizes transactions and selects one to be serviced. If the selected transaction is waiting for row address strobe (RAS) precharge, and another higher priority transaction is initiated, the scheduler deselects the previously chosen transaction and selects the higher priority transaction. 3.2.2.
3.3 21071-DA Functional Overview The 21071-DA is a bridge between the PCI local bus and the 21064A microprocessor and its L2 cache and memory. The 21071-DA contains all control functions of the bridge and some data path functions. Other data path functions reside in the 21071-BA. The 21071-DA can be divided into two major sections: the sysBus (processor, memory) interface and the PCI interface. The following sections describe the sysBus and PCI interface features.
3.3.1 sysBus Interface The sysBus interface includes the sysBus control state machine, the address decode for CPU-initiated transactions, buffering for CPU-initiated transactions, and the 21071-DA control and status registers. 3.3.1.1 Address Decode The 21071-DA provides logic for translating and extending between the 21064A 34-bit physical address space and the 32-bit PCI address space.
3.3.2.2 DMA Write Buffer The PCI interface has a write buffer for buffering DMA write data. The DMA write buffer is made up of four entries. Each entry contains the cache-line address, eight longwords of data, the byte enables corresponding to each longword, and a valid bit for the entry. The untranslated PCI address is stored in the DMA write buffer. Address translation is performed when the particular entry is unloaded from the DMA write buffer.
3.3.2.5 PCI Burst Order PCI address bits ad<1:0> specify the burst ordering requested by the master during memory transactions. When the 21071-DA is a master of the PCI, it will always indicate a linear incrementing burst order (ad<1:0> = 0) on read and write transactions. On DMA transactions, the 21071-DA supports burst transfers only when a linear-incrementing burst order is specified.
The 21071-DA also supports PCI bus parking during reset. If the iogrant signal is asserted by the PCI arbiter (req_l is always tristated by the 21071-DA during reset), the 21071-DA will drive ad<31:0>, cbe<3:0>, and (one clock cycle later) par. When iogrant is deasserted, the 21071-DA tristates these signals. 3.3.2.9 PCI Retry Timeout The 21071-DA implements a timeout mechanism to terminate CPU-initiated transactions that do not complete on the PCI because of too many disconnects or retries.
• I/O transfers from the CPU to the PCI or to 21071-DA CSRs are performed in order. This policy guarantees a coherent view of PCI I/O space from the CPU. • The 21071-DA flushes DMA write data to memory before acknowledging a barrier command from the CPU. Because explicit ordering commands are absent on the PCI, the MB instruction is used to order CPU and DMA accesses. • The 21071-DA also flushes the I/O write buffer to the PCI before acknowledging a barrier command.
3.3.2.14 Guaranteed Access-Time Mode The Intel 82378ZB ISA bridge provides three sideband signals (flushreq_l, memreq_l, and memack_l) to provide mechanisms for flushing system write buffers and to allow a guaranteed access time of 2.1 s to a master on the ISA bus. The flushreq_l and memreq_l signals are outputs from the bridge; memack_l is an input to the bridge. Note Guaranteed access-time mode is not supported on the AlphaPC64. 3.3.2.
3.4 21071-BA Functional Overview This section describes the data bus configurations and provides a functional overview of the 21071-BA. Figure 3–7 shows a block diagram of the 21071-BA. Figure 3–7 DECchip 21071-BA Block Diagram Memory Read Buffer sysData <127:0> Memory Write Buffer Merge I/O Read Buffer memData <127:0> PAD Latch Parity Check DMA Read Buffer DMA Write Buffer I/O Write Buffer Parity Generator epiData <31:0> 75% LJ03948A.AI 3.4.
3.4.2 memData Bus With a memData bus of 128 bits, four 21071-BA chips are required, that is: • 21071-BA0 connects to longword 0 (memdata<31:0>) • 21071-BA1 connects to longword 1 (memdata<63:32>) • 21071-BA2 connects to longword 2 (memdata<95:64>) • 21071-BA3 connects to longword 3 (memdata<127:64>) 3.4.3 epiData Bus Each 21071-BA has 32 epiData bus pins. The epiData pins of the 21071-BA chips are tied together to form a 32-bit epiData bus. 3.4.
3.4.7 DMA Write Buffer The DMA write buffer has four entries. Each entry contains four longwords for each 21071-BA and corresponding byte masks. However, only half the storage for each entry is used. The extra storage is not accessible. The DMA write buffer is loaded by the 21071-DA and is unloaded by the 21071-CA during a DMA write transaction on the sysBus.
3.5 Error Handling The first error causes CSR error bits and the associated error address register to be set and locked. If another error occurs, only the lost error bit is set and int_hw0 is asserted to interrupt the processor. The int_hw0 signal is held asserted as long as the corresponding error bit is set. The PCI error address register (PEAR) logs addresses sent out or received on the PCI. The sysBus error address register (SEAR) logs the address that was sent out or received on the sysBus.
3.6 Clock Subsystem The system clocks can be divided into three areas: the input clocks required by the CPU, CPU clock distribution to the system logic, and miscellaneous oscillators and clocks required for the peripheral interfaces and functions. The 21064A CPU clock input is provided by a TriQuint phase-locked loop (PLL) clock oscillator. 3.6.
Assume a TriQuint 500-MHz differential clock is supplied to the CPU. The CPU divides the clock by 2, generating its internal clock operating at 250 MHz. The internal clock is further divided by the CPU to generate the system clock (sysclkout1). The system clock divisor can be programmed over a range from 2 to 17 as specified in Table 3–2.
3.6.2 System Clock Distribution Figure 3–9 shows the primary clock distribution network for both phase-locked loop (PLL) devices. The major module clock, sysclkout1, is developed by the 21064A. It is sent to U39, a PLL clock device (AMCC S4402).
Figure 3–9 Primary Clock Distribution Network U39 21064A sysclkout1 AMCC S4402 sysclk_pll90 sysclk_pll0 sysclk_pll0_2x U38 74FCT 805CT pciclk_sio sysclk_pll90 Buffer 1 33-MHz Clocks (Shifted 90°) pciclk_slot<3:0> clk1x2_dec<1:4> sysclk_pll0_2x Buffer 2 66-MHz Clocks clk1x2_com_epic U37 74FCT 805CT clk2xref_pal clk2xref_dec1_dec2 Buffer 1 clk2xref_dec3_dec4 clk2xref_com_epic 33-MHz Clocks (Shifted 90°) pciclk_epic clk1_pal sysclk_pll0 Buffer 2 33-MHz Clock to L2 Cache PAL clk1_fb 33-MHz Fee
U40 generates six 66-MHz clock signals, which are distributed as shown in Table 3–3. Table 3–3 Distribution of 66-MHz Clock Signals Clock Signal Name Destination clk1x2_dec1 21071-BA0 (AlphaPC64.20) clk1x2_dec2 21071-BA1 (AlphaPC64.20) clk1x2_dec3 21071-BA2 (AlphaPC64.21) clk1x2_dec4 21071-BA3 (AlphaPC64.21) clk1x2_com_epic 21071-DA (AlphaPC64.6, AlphaPC64.23) U39 generates thirteen 33-MHz clock signals. These 33-MHz clock signals are shifted 90 degrees.
U40 also generates two 33-MHz clock signals, which are distributed as shown in Table 3–5. Table 3–5 Distribution of 33-MHz Clock Signals Clock Signal Name Destination clk1_pal U25 (L2 cache PAL) (AlphaPC64.7) clk1_fb U39 (provide feedback to S4402 PLL) (AlphaPC64.5) There are two additional oscillators that provide 14.3-MHz and 24-MHz clocks for the AlphaPC64, as shown in Figure 3–10. Figure 3–10 Buffered Clock Distribution Network clkb pciclk_sio AlphaPC64.5 14.
3.7 PCI Interrupts and Arbitration The following subsections describe the PCI interrupt and arbitration (arbiter) logic. 3.7.1 System Interrupts Figure 3–11 shows the AlphaPC64 interrupt logic. Interrupt logic is implemented in two programmable logic devices (PLDs), MACH210–20 and AMD22V10–25, shown on AlphaPC64.34. The PLDs allow each PCI and Saturn IO (SIO) chip interrupt to be individually masked. The PLDs also allow the current state of the interrupt lines to be read.
Figure 3–11 Interrupt Control and PCI Arbitration sys_irq0 21071-DA System Interrupt PLDs pci_isa_irq<0> AlphaPC64.34 pci_inta<3:0> pci_intb<3:0> pci_intc<3:0> pci_intd<3:0> rtc_irq_l<1> nmi <2> PCI Bus AlphaPC64.4 sio_int cpu_irq5, <2:0> pci_req_s0_l MUX pci_gnt_s0_l PCI Slot 0 pci_req_s1_l PCI Slot 1 pci_gnt_s1_l CPU irq_resetd_l jmp_irq<2:0> PCI-to-ISA Bridge pci_req_s2_l PCI Slot 2 pci_gnt_s2_l Clock Multiplier Jumpers pci_req_s3_l PCI Slot 3 pci_gnt_s3_l AlphaPC64.
Three jumpers (J14, J15, and J16) connect to one side of the multiplexer. The jumper configuration sets the CPU clock multiplier value through the IRQ inputs during reset. The ISA bus interrupts (IRQ0 through IRQ8 and IRQ12 through IRQ14) are all nested through the SIO and then into the CPU.
Each interrupt can be individually masked by setting the appropriate bit in the mask register. An interrupt is disabled by writing a 1 to the desired position in the mask register. An interrupt is enabled by writing a 0. For example, bit <7> set in interrupt mask register 1 indicates that the INTB2 interrupt is disabled. There are three mask registers located at ISA addresses 804, 805, and 806.
3.8 PCI Devices The AlphaPC64 uses the PCI bus as the main I/O bus for the majority of peripheral functions. The board implements the ISA bus as an expansion bus for system support functions and peripheral devices. 3.8.1 Intel Saturn IO Chip The SIO chip provides the bridge between the PCI bus and the Industry Standard Architecture (ISA) bus.
3.9 ISA Devices Figure 3–13 shows the AlphaPC64 ISA bus implementation with peripheral devices and connectors. Also shown is the utility bus with system support devices. Figure 3–13 ISA Devices PCI Bus la<23:17> sd<15:0> ubus<7:0> sd<7:0> Transceiver AlphaPC64.33 PCI-to-ISA Bridge 82378ZB Diskette J24 AlphaPC64.30 Combination Chip 87312 Parallel J25 AlphaPC64.29 Flash ROM 1M x 8 TOY 1287 COM1 J32 Keyboard Mouse 8242 ISA Slot 0 ISA Slot 1 ISA Slot 2 J17 J18 J19 AlphaPC64.
The 8242 is an Intel UPI-42AH universal peripheral interface. It is an 8-bit slave microcontroller with 2KB of ROM and 256 bytes of RAM that has been preprogrammed with a keyboard BIOS for standard scan codes. Refer to either of the following Intel documents for additional information: • UPI™-41AH/42AH Universal Peripheral Interface 8-Bit Slave Microcontroller • Peripheral Components 3.9.
3.9.3 Time-of-Year Clock The Dallas DS1287 chip, located on the ISA utility bus, provides the time-ofyear (TOY) function. It is contained in a plastic 24-pin dual inline package (DIP). The DS1287 is designed with onchip RAM, a lithium energy source, a quartz crystal, and write-protection circuitry (see Figure 3–13).
Refer to the Intel Flash Memory document for additional information about pin assignments and signal descriptions, register descriptions, and a functional description (including timing, electrical characteristics, and mechanical data). 3.9.5 ISA Expansion Slots Three ISA expansion slots are provided for plug-in ISA peripherals. One of the slots is shared with the PCI and can be used for a PCI or ISA device. 3.10 Serial ROM The 21064A uses a serial ROM (SROM) for its initialization code.
Figure 3–14 SROM Serial Port srom_d srom_oe_l real_srom_d SROM 21064A srom_clk AlphaPC64.2 AlphaPC64.3 srom_clk_l srom_oe_l J2 IRQMUX AlphaPC64.34 gnd test_srom_d_l test_srom_d AlphaPC64.3 LJ04142A.AI After the SROM code has been read into the Icache, the 21064A SROM port can be used as a software controlled serial port.
Figure 3–15 dc Power Distribution Power Connectors: AlphaPC64.38 J31 1 p_dcok 3 +12 V dc 4 -12 V dc IC Devices Clocks PCI Slots ISA Slots J29 3 4 -5 V dc AlphaPC64.27 AlphaPC64.24-25 AlphaPC64.2 Vdd 5 6 3 V dc Logic Fan J28 1 3 V dc 21064A 2 3 AlphaPC64.2 4 J31 5 2 Vdd 6 5 Ground 6 J27 1 Ground 2 J29 3 4 3 V dc 5 1 2 6 LJ04143B.
A TL7702B power monitor senses the +3-V dc input to ensure that it is stable before the 21064A inputs and I/O pins are driven. Any device that drives the 21064A has a tristate output controlled by the power monitor output. If the +3-V dc output fails, the power monitor enables sense_dis, which is applied to the reset logic (AlphaPC64.36). The reset logic generates a group of reset functions to the 21064A and the remainder of the system, including PCI devices (see Section 3.12). 3.
Figure 3–16 System Reset and Initialization dc Power J31 p_dcok OR Gate b_dcok Fan Sensor J14 fan_ok_l AlphaPC64.37 Reset Switch button_1 J3 OR Gate pre_reset p_dcok AlphaPC64.37 AlphaPC64.4 U29 pre_reset +3 V dc Power Sense AlphaPC64.4 sense_dis NOR Gate rst_l 74ACT244 sys_reset1_l sys_reset2_l sys_reset3_l sys_reset4_l AlphaPC64.37 Reset Functions: - PCI-to-ISA Bridge - PCI Interrupt Controller - 21071-DA - 21071-CA - 21071-BA - 21064A cpu_dcok b_dcok cpu_reset AlphaPC64.
3.13.2 Flash ROM Code The AlphaPC64 includes an industry-standard, 1MB flash ROM that is programmed to include the debug monitor code (AlphaPC64.35) during manufacture. The user can develop code on a host system and program it into the ROM by loading it into the AlphaPC64 through the serial or optional Ethernet ports.
4 System Address Mapping This chapter describes the mapping of the 34-bit processor physical address space into memory and I/O space addresses. It also includes the translations of the processor-initiated address into a PCI address, and PCI-initiated addresses into physical memory addresses. 4.
Figure 4–1 sysBus Address Map 0 0000 0000 Cacheable Memory Space 0 FFFF FFFF 1 0000 0000 Noncacheable Memory Space 1 7FFF FFFF 1 8000 0000 21071-CA CSR Space 1 9FFF FFFF 1 A000 0000 21071-DA CSR Space 1 AFFF FFFF 1 B000 0000 PCI Interrupt Acknowledge Special Cycle Space 1 BFFF FFFF 1 C000 0000 PCI Sparse I/O Space 1 DFFF FFFF 1 E000 0000 PCI Configuration Space 1 FFFF FFFF 2 0000 0000 PCI Sparse Memory Space 2 7FFF FFFF 3 0000 0000 PCI Dense Memory Space 3 FFFF FFFF LJ-03952.
Table 4–1 sysBus Address Space Description sysAdr <33:32> sysAdr <31:28> 00 xxxx Address Space Description Cacheable memory space Accessed by the CPU instruction stream (Istream) or data stream (Dstream). Accessed by DMA. The 21071-DA does not respond to addresses in this space. 01 0xxx Noncacheable memory space Accessed by the CPU (Istream or Dstream). Accessed by DMA. Can be used for a frame buffer on the DRAM bus. The 21071-DA does not respond to addresses in this space.
Table 4–1 (Cont.) sysBus Address Space Description sysAdr <33:32> sysAdr <31:28> 01 xxxx Address Space Description PCI sparse memory space 128MB addressable PCI space. The lower address bits are used to determine byte masks and transaction length information. The 4GB space is reduced to a 128MB sparse space. Use this space when byte or word granularity is required. Read or write length is no more than a quadword. Reading other than the requested data is harmful. Prefetching read data is prohibited.
4.1.3 DECchip 21071-CA CSR Space (1 8000 0000 to 1 9FFF FFFF) The DECchip 21071-CA responds to all CSR accesses in this space. Table 4–2 specifies the registers and associated register addresses. Appendix A contains the register descriptions.
Table 4–2 (Cont.
4.1.4 DECchip 21071-DA CSR Space (1 A000 0000 to 1 AFFF FFFF) The DECchip 21071-DA responds to all accesses in this space. Table 4–3 specifies the registers and associated register addresses. Appendix A contains the register descriptions.
Table 4–3 (Cont.) DECchip 21071-DA CSR Register Addresses Address16 Register Name 1 A000 0300 TLB 0 data register 1 A000 0320 TLB 1 data register 1 A000 0340 TLB 2 data register 1 A000 0360 TLB 3 data register 1 A000 0380 TLB 4 data register 1 A000 03A0 TLB 5 data register 1 A000 03C0 TLB 6 data register 1 A000 03E0 TLB 7 data register 1 A000 0400 Translation buffer invalidate all register (TBIA) 4.1.
4.1.6 PCI Sparse I/O Space (1 C000 0000 to 1 DFFF FFFF) The PCI sparse I/O space is similar to the PCI sparse memory space. This 512MB sysBus address space maps to 16MB of PCI I/O address space. A read or write transaction to this space causes a PCI I/O read or PCI I/O write command respectively. Bits sysBus<33:29> identify the various address spaces on the sysBus. Bits sysBus<6:3> generate the length of the PCI transaction in bytes, the byte enables, and ad<2:0> on the PCI (see Table 4–4).
Figure 4–2 PCI Sparse I/O Space Address Translation 33 29 28 23 22 08 07 05 04 03 02 00 sysBus Address 0 1 1 1 0 0 0 0 0 0 0 Length in Bytes HAXR0 Byte Offset 31 24 23 03 02 00 PCI I/O Address 0 0 0 0 0 0 0 0 Address Translation for Lower 256KB of PCI I/O Space 33 29 28 0 1 1 1 0 31 24 23 23 22 08 07 05 04 03 02 00 sysBus Address Nonzero HAXR2 Length in Bytes 00 Byte Offset 31 24 23 03 02 00 PCI Memory Space Address Translation for Remaining 64MB - 64KB of PCI Memory Space L
Table 4–4 PCI Sparse I/O Space Byte Enable Generation Length CPU Address <6:5> CPU Address <4:3> PCI Byte Enable1 PCI ad<2:0> Byte 00 00 1110 CPU address<7>, 00 01 00 1101 CPU address<7>, 01 10 00 1011 CPU address<7>, 10 Word Tribyte Longword Longword 11 00 0111 CPU address<7>, 11 00 01 1100 CPU address<7>, 00 01 01 1001 CPU address<7>, 01 10 01 0011 11 01 Illegal 00 10 1000 01 10 0001 — CPU address<7>, 00 CPU address<7>, 01 2 — 10 10 Illegal 11 10 Illeg
4.1.7 PCI Configuration Space (1 E000 0000 to 1 FFFF FFFF) A read or write access to this space causes a configuration read or write cycle on the PCI. There are two classes of targets: devices on the primary PCI bus and devices on the secondary PCI buses that are accessed through PCI-to-PCI bridge chips. During PCI configuration cycles, the meanings of the address fields vary depending on the intended target of the configuration cycle.
Table 4–6 translates sysAdr<20:16> to PCI primary bus addresses.
4.1.7.1 PCI Configuration Cycles to Primary Bus Targets Primary PCI bus devices are selected during a PCI configuration cycle if their IDSEL# pin is asserted, if the PCI bus command indicates a configuration read or write transaction, and if ad<1:0> are 00. Bits ad<7:2>, which are taken from sysAdr<12:7>, select a longword register in the device’s 256-byte configuration address space. Configuration accesses can use byte masks, which may be derived by following the method shown in Table 4–4.
If the bus number of the configuration cycle matches the bus number of the bridge chip secondary PCI interface, it will intercept the configuration cycle, decode it, and generate a PCI configuration cycle with ad<1:0> equal to 01 on its secondary PCI interface. If the bus number is within the range of bus numbers that may exist hierarchically behind its secondary PCI interface, the PCI configuration cycle passes, unmodified (leaving ad<1:0> = 01), through the bridge.
Figure 4–3 shows the sysBus to PCI memory address translation. Table 4–7 shows the generation of the byte enables and PCI address ad<2:0> from sysBus<6:3>.
Table 4–7 PCI Sparse Memory Space Byte Enable Generation Length PCI Byte CPU CPU Address<6:5> Address<4:3> Enable1 PCI ad<2:0>2 Byte 00 00 1110 CPU address<7>, 00 01 00 1101 CPU address<7>, 00 10 00 1011 CPU address<7>, 00 11 00 0111 CPU address<7>, 00 00 01 1100 CPU address<7>, 00 01 01 1001 CPU address<7>, 00 10 01 0011 CPU address<7>, 00 11 01 Illegal3 — 00 10 1000 CPU address<7>, 00 01 10 0001 Word Tribyte Longword CPU address<7>, 00 3 10 10 Illegal — 1
Accesses in this space are no more than a quadword. Software must ensure that the processor does not merge consecutive write transactions in its write buffers by using memory barriers after each write transaction. Architecturally, if a byte, word, tribyte, or longword is written on the PCI, an STL instruction must be executed to the lower longword in the corresponding quadword address. An STQ or STL instruction to the upper longword is not allowed.
The address generation in dense space is as follows: • Bits sysBus<31:5> are sent out on ad<31:5>. • On read transactions, ad<4:3> is generated from cpucwmask<1:0>; ad<2> is always 0. • On write transactions, ad<4:2> is generated from cpucwmask<7:0>. If the lower longword is to be written, ad<2> is 0; if the lower longword is masked out and the upper longword is to be written, ad<2> is 1. The number of longwords written on the PCI is directly obtained from cpucwmask<7:0>.
Table 4–8 PCI Target Window Enables PCI_MASK<31:20>1 Window Size Value of n2 0000 0000 0000 1MB 20 0000 0000 0001 2MB 21 0000 0000 0011 4MB 22 0000 0000 0111 8MB 23 0000 0000 1111 16MB 24 0000 0001 1111 32MB 25 0000 0011 1111 64MB 26 0000 0111 1111 128MB 27 0000 1111 1111 256MB 28 0001 1111 1111 512MB 29 0011 1111 1111 1GB 30 0111 1111 1111 2GB 31 1111 1111 1111 4GB3 32 1 Combinations of bits not shown in PCI_MASK<31:20> are not supported.
Note The window base addresses must be on naturally aligned address boundaries, depending on the size of the window. Figure 4–4 PCI Target Window Compare Scheme n n -1 31 PCI Address 20 19 13 12 Peripheral Page Number Compare n n -1 31 PCI Base Register Offset Hit 20 XXX n n -1 31 PCI Mask Register 00 0000000 20 111 (Determines n ) LJ-03955.
If SGEN is cleared, the DMA address is direct mapped. The translated address is generated by concatenating bits from the matching window translated base register with bits from the incoming PCI address. The PCI mask register determines which bits of the translated base register and PCI address are used to generate the translated address as shown in Table 4–9. Note that the unused bits of the translated base register must be cleared for correct operation.
Each SG map entry maps an 8KB page of PCI address space into an 8KB page of processor address space. Each SG map entry is a quadword. Each entry has a valid bit in position 0. Address bit ad<13> is at bit position 1 of the map entry. Because the 21072 implements only valid memory addresses up to 6GB, bits ad<63:21> of the SG map entry must be programmed to 0. Bits ad<21:1> of the SG entry generate the physical page address.
Table 4–10 Scatter-Gather Map Address PCI_MASK<31:20> SG Map Table Size SG Map Address<32:3> 0000 0000 0000 1KB T_BASE<32:10>:PCI ad<19:13> 0000 0000 0001 2KB T_BASE<32:11>:PCI ad<20:13> 0000 0000 0011 4KB T_BASE<32:12>:PCI ad<21:13> 0000 0000 0111 8KB T_BASE<32:13>:PCI ad<22:13> 0000 0000 1111 16KB T_BASE<32:14>:PCI ad<23:13> 0000 0001 1111 32KB T_BASE<32:15>:PCI ad<24:13> 0000 0011 1111 64KB T_BASE<32:16>:PCI ad<25:13> 0000 0111 1111 128KB T_BASE<32:17>:PCI ad<26:13> 0000 1111 1
Figure 4–6 SG Map Translation of PCI to SysBus Address n 31 PCI Address 13 12 Peripheral Page Number 05 04 00 Offset Compare sysBus Base Address (Translated Base Register) Scatter-Gather Map Address Driven on sysBus n -10 n -11 33 07 T_BASE 0000 n -10 n -11 33 20 03 01 Scatter-Gather Entry Scatter-Gather Map in Main Memory Physical Memory Location Driven on sysBus 33 32 13 12 sysBus Page Number 05 Offset LJ03957A.
5 Board Requirements and Parameters This chapter describes the evaluation board power and environmental requirements, and physical board parameters. 5.1 Power Requirements The AlphaPC64 derives its main dc power from a user-supplied, industrystandard PC power supply. The board has a total power dissipation of 96.2 W, excluding PCI and ISA devices. Table 5–1 lists the power requirements of each dc supply voltage. The power supply must supply signal p_dcok to the system reset logic. Refer to Section 3.
5.2 Environmental Characteristics The AlphaPC64 board environmental characteristics are: • Operating temperature range of 10°C to 40°C (50°F to 104°F) • Storage temperature range of –55°C to 125°C (–67°F to 257°F) 5.3 Physical Board Parameters The AlphaPC64 board consists of a 6-layer printed-wiring board. The board is populated with integrated circuit packages together with supporting active and passive components. The AlphaPC64 is a baby-AT-size board with the following dimensions: • Width: 22.
Figure 5–1 Major Board Component Layout 41 39 37 38 43 40 42 44 45 46 51 47 48 50 49 36 6 28 27 30 24 1 35 34 29 7 33 8 23 2 26 25 22 31 32 17 16 9 4 10 21 15 11 20 14 19 13 3 12 5 18 Scale = 90% LJ-04460.
Table 5–2 Major Board Component Descriptions Number Device Component Description 1 U36 Alpha 21064A–275 microprocessor—431 PGA, DC290A, 275 MHz 2 U24 DECchip 21071–BA0, 208-pin PQFP, ASIC 3 U8 DECchip 21071–BA1, 208-pin PQFP, ASIC 4 U13 DECchip 21071–BA2, 208-pin PQFP, ASIC 5 U2 DECchip 21071–BA3, 208-pin PQFP, ASIC 6 U35 DECchip 21071–DA, 208-pin PQFP, ASIC 7 U31 DECchip 21071–CA, 208-pin PQFP, ASIC 8, 9 U25, 17 PALCE16V8–5, 5-ns, 125-mA, 20-pin PLCC 10, 11, 12 U14, U9, U5 74FC
Table 5–2 (Cont.
A System Register Descriptions This appendix describes the control and status registers (CSRs) of the DECchip 21071-CA (Sections A.1 and A.1.8) and DECchip 21071-DA (Section A.2). A.1 DECchip 21071-CA CSR Descriptions The CSRs are 16 bits wide and are addressed on cache-line boundaries. Write transactions to read-only registers could result in UNPREDICTABLE behavior; read transactions are nondestructive. Only zeros should be written to unspecified bits within a CSR.
Figure A–1 General Control Register 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 MBZ MBZ BC_BADAP BC_FRCP BC_FRCV BC_FRCD BC_FRCTAG BC_IGNTAG BC_LONGWR BC_NOALLOC BC_EN WIDEMEM MBZ SYSARB MBZ LJ-04178.AI Table A–1 General Control Register Field Name Type <15:14> Reserved MBZ Description — 1 <13> BC_BADAP RW, 0 L2 cache force bad address parity. When set, the tag address parity will be loaded as bad (independent of the BC_FRCTAG bit). <12> BC_FRCP RW, 0 L2 cache force parity.
Table A–1 (Cont.) General Control Register Field Name Type Description <9> BC_FRCTAG RW, 0 L2 cache force tag. When set, the LE cache will be probed for victims, and the line will be invalidated using the values in the BC_FRCD, BC_FRCV, and BC_FRCP fields. CSRs will be used as the tag controls. Although the line is invalidated (assuming BC_FRCV is reset), the data is loaded into the cache, and will be returned to the CPU as cacheable.
A.1.2 Error and Diagnostic Status Register The error and diagnostic register is shown in Figure A–2 and is defined in Table A–2. The register contains read-only status information for diagnostics and error analysis. The occurrence of an error sets one or more error bits (BC_TAPERR, BC_TCPERR, NXMERR) and locks the address of the error. After the address is locked, any additional error will set LOSTERR and will not affect the address or other error bits (BC_TAPERR, BC_TCPERR, NXMERR).
Table A–2 (Cont.) Error and Diagnostic Status Register Field Name Type Description <13> PASS 2 RO Chip version reads low on pass 1 and high on pass 2. <12:9> Reserved MBZ — <8:6> CREQCAUSE RO Cycle request that caused error. Indicates the DMA or CPU cycle request type that caused the error. Contains a copy of either the cpucreq or iocmd signal lines, depending on DMACAUSE<4>. Locked with the error address. Only valid when an error is indicated on BC_TAPERR, BC_TCPERR, or MEMERR.
A.1.3 Tag Enable Register The tag enable register, shown in Figure A–3, indicates which bits of the cache tag are to be compared with sysadr<33:5>. If a bit is 1, the corresponding bits in sysadr<33:5> and systag<31:17> are compared. If a bit is 0, there is no comparison for those bits, and the systag bit is assumed to be tied low on the module (through a resistor). Bits <15:1> in the register represent systag<31:17>. This register is not initialized.
Table A–3 Cache Size Tag Enable Values TAGEN<15:0> Compared Bits 0000 0000 0000 00001 None Cache Size 4GB 1000 0000 0000 0000 <31> 2GB 1100 0000 0000 0000 <31:30> 1GB 1110 0000 0000 0000 <31:29> 512MB 1111 0000 0000 0000 <31:28> 256MB 1111 1000 0000 0000 <31:27> 128MB 1111 1100 0000 0000 <31:26> 64MB 1111 1110 0000 0000 <31:25> 32MB 1111 1111 0000 0000 <31:24> 16MB 1111 1111 1000 0000 <31:23> 8MB 1111 1111 1100 0000 <31:22> 4MB 1111 1111 1110 0000 <31:21> 2MB 1111 1111
Table A–4 (Cont.) Maximum Memory Tag Enable Values TAGEN<15:0> Compared Bits 0000 0011 1111 1110 <25:17> 64MB 0000 0001 1111 1110 <24:17> 32MB 0000 0000 1111 1110 <23:17> 16MB 0000 0000 0111 1110 <22:17> 8MB 0000 0000 0011 1110 <21:17> 4MB 0000 0000 0000 1110 <19:17> 1MB 0000 0000 0000 0110 <18:17> 512KB 0000 0000 0000 0010 <17> 256KB 0000 0000 0000 0000 None 128KB Memory Size A.1.4 Error Low Address Register The error low address register is shown in Figure A–4.
Figure A–5 Error High Address Register 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 MBZ ERR_HADR<33:21> LJ-04182.AI A.1.6 LDx_L Low Address Register The LDx_L low address register is shown in Figure A–6. The register stores the low-order bits of the last locked address. Bits <15:0> in the register represent sysadr<20:5>. This register is read-only and is not initialized. Figure A–6 LDx_L Low Address Register 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 LDXL_LARD<20:5> LJ-04183.AI A.1.
A.1.8 Memory Control Registers This section describes and defines 21071-CA registers that control memory configuration and timing. Each bank set of memory has one configuration register and two timing registers. The global timing register and refresh timing register apply to all bank sets. The video frame pointer is used for video transactions to bank set 8. A.1.8.1 Video Frame Pointer Register The video frame pointer register is shown in Figure A–8 and is defined in Table A–5.
Table A–5 (Cont.) Video Frame Pointer Register Field Name Type Description <4:0> VFP_COLADR RW Video frame column address pointer. Used as column address <6:2> for all serial register loads. A.1.8.2 Presence Detect Low-Data Register The presence detect low-data register is shown in Figure A–9. The register stores the low-order bits of the presence detect data that was shifted in after reset. Bits <15:0> in the register represent data bits <15:0> that were shifted in.
A.1.8.3 Presence Detect High-Data Register The presence detect high-data register is shown in Figure A–10. The register stores the high-order bits of the presence detect data that was shifted in after reset. Bits <15:0> in the register represent data bits <31:16> that were shifted in. Note After deassertion of reset, it takes 148 system clock cycles for this data to become valid. Figure A–10 Presence Detect High-Data Register 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PRES_DET<31:16> LJ-04187.AI A.
The number of bits that are compared depends on the size of the corresponding bank set. Bank sets 7 to 0 have an 11-bit field, limiting the minimum DRAM bank set size to 8MB. Bits <15:5> in the register correspond to sysadr<33:23>. Bank set 8, which can contain video RAMs and has a minimum size of 1MB, has the same 11-bit field, where bits <15:5> in the register correspond to sysadr<33:23> while sysadr<22:20> are compared with zero.
Bank Set 0 to 7 Configuration Registers Bank set 0 to 7 configuration registers have the same format and also have the same limits on bank set size and type of DRAMs used. With the exception of the valid bit, these registers are not initialized. Bank set 0 to 7 registers are shown in Figure A–12 and are defined in Table A–6. Figure A–12 Bank Set 0 to 7 Configuration Register 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 MBZ S0_COLSEL S0_SUBENA S0_SIZE S0_VALID LJ-04189.
Table A–6 (Cont.) Bank Set 0 to 7 Configuration Register Field Name Type Description <5> S0_SUBENA RW, 0 Enable subbanks. When set, subbanks are enabled and are determined according to S0_SIZE. When clear, subbanks are disabled, and the <3:0>_rasb0_l pins will be asserted only during refreshes. <4:1> S0_SIZE RW Bank set 8 size in megabytes.
Figure A–13 Bank Set 8 Configuration Register 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 MBZ S8_CHECK S8_COLSEL S8_SUBENA S8_SIZE S8_VALID LJ-04190.AI Table A–7 Bank Set 8 Configuration Register Field Name Type Description <15:10> Reserved MBZ — <9> S8_CHECK RW, 0 Enable parity checking. When set, accesses to bank set 8 will have their parity checked, as with other bank sets. When clear, parity will not be checked. When clear, bank set 8 must be mapped into noncacheable space.
Table A–7 (Cont.) Bank Set 8 Configuration Register Field Name Type Description <5> S8_SUBENA RW, 0 Enable subbanks. When set, subbanks are enabled and determined according to S8_SIZE. When clear, subbanks are disabled, and the b<1:0>_rasb0_l pins will be asserted only during refresh. <4:1> S8_SIZE RW, 0 Bank set 8 size. Indicates the size of the bank set to determine which bits are used in comparing the base address with the physical address and for selecting the subset (if S8_SUBENA is set).
On reset, all the parameters are set to the maximum value. This may not result in correct operation on the memory interface. Therefore, the timing registers should be programmed by software before setting the corresponding bank set valid bit in the configuration register. All the timing parameters are in multiples of memclk cycles. Most of the timing parameters in timing registers A and B have a minimum value that is added to the programmed value.
Table A–8 (Cont.) Bank Set Timing Register A Field Name Type Description <11:9> S8_RDLYROW RW, 1 Read delay from row address. Delay from row address to latching first valid read data. <8:7> S8_COLHOLD RW, 1 P rogrammed value = desired value 0 4. Column hold. Column hold (tCAH ) from b0_cas<1:0>_l assertion. Used to determine when the current column address can be changed to the next column or row address. P rogrammed value = desired value 0 1. <6:4> S8_COLSETUP RW, 0 Column address setup.
Figure A–15 Bank Set Timing Register B 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 MBZ S8_WHOLD0COL S8_WHOLD0ROW S8_TCP S8_WTCAS S8_RTCAS LJ-04192.
Table A–9 Bank Set Timing Register B Field Name Type Description <15:14> Reserved MBZ — <13:11> S8_WHOLD0COL RW, 1 Write hold time from column address. Used only for the first data when starting in page mode. Write data is valid with the column address and is held valid S8_WHOLD0COL + 2 cycles after the column address. P rogrammed value = desired value 0 2. <10:8> S8_WHOLD0ROW RW, 1 Write hold time from row address. Hold time of first write data from first row address.
A.1.8.7 Global Timing Register The global timing register contains parameters that are common to all memory bank sets. Each parameter counts memclk cycles. All pins on the memory interface are referenced to memclk rising. The global timing register is shown in Figure A–16 and is defined in Table A–10. Figure A–16 Global Timing Register 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 MBZ GTR_MAX_RAS_WIDTH GTR_RP LJ-04193.
A.1.8.8 Refresh Timing Register The refresh timing register contains refresh timing information used to simultaneously refresh all bank sets using CAS-RAS refresh. Therefore, these parameters should be programmed to the most conservative values across all sets. All the timing parameters are in multiples of memclk cycles. The parameters have a minimum value that is added to the programmed value.
Table A–11 (Cont.) Refresh Timing Register Field Name Type Description <6:4> REF_RASWIDTH RW, 1 Refresh RAS width. Refresh RAS assertion width from b<3:0>_ras0_l assertion to b<3:0>_ras0_l deassertion. b<3:0>_cas0_l is deasserted with b<3:0>_ras0_l for refresh. Corresponds to DRAM parameter tRAS . <3:1> REF_CAS2RAS RW, 1 P rogrammed value = desired value 0 3. Refresh CAS assertion to RAS assertion cycles. Corresponds to DRAM parameter tCSR . P rogrammed value = desired value 0 2.
A.2.2 Diagnostic Control and Status Register The diagnostic control and status register (DCSR) provides control of operational and diagnostic modes, and it reports status and error conditions. The register is shown in Figure A–18 and is defined in Table A–12.
Table A–12 Diagnostic Control and Status Register Field Name Type Description <31> PASS2 RO Pass 2. Chip version reads low on pass 1 and high on pass 2. <30:22> Reserved MBZ — <21:18> PCMD RO PCI command. This field indicates the PCI type when a PCI-initiated error is logged in the DCSR. The field is valid only when IPTL, NDEV, TABT, and IOPE are set. <17:16> D_BYP<1:0> RW, 0 Disable read bypass.
Table A–12 (Cont.) Diagnostic Control and Status Register Field Name Type Description <10> TABT RWC, 0 Target abort. This bit is set when a PCI slave device ends an I/O read or write transaction using the PCI target abort protocol. Bits ad<31:0> for this transaction are logged in the PCI error address register. <9> IOPE RWC, 0 I/O parity error. This bit is set when a parity error occurs in the data phase of an I/O read or write transaction.
Table A–12 (Cont.) Diagnostic Control and Status Register Field Name Type Description <0> TENB RW, 0 TLB enable. When this bit is set, the entire TLB is enabled. When the bit is cleared, the TLB will be turned off and subsequent scatter-gather read transactions will not result in allocation of TLB entries. Entries that were valid when the TENB bit was cleared will remain valid. To invalidate entries, software must write to the TBIA register.
A.2.3 sysBus Error Address Register The sysBus error address register holds the sysBus address that was being used when an error happened. The register is shown in Figure A–19 and is defined in Table A–14. Figure A–19 sysBus Error Address Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 SYS_ERR<33:5> MBZ LJ-04196.AI Table A–14 sysBus Error Address Register Field Name Type Description <31:3> SYS_ERR<33:5> RO sysBus error address.
A.2.4 PCI Error Address Register The PCI error address register holds the PCI address ad<31:0> that was being used when an error happened. The register is shown in Figure A–20 and is defined in Table A–15. Figure A–20 PCI Error Address Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PCI_ERR<31:0> LJ-04197.AI Table A–15 PCI Error Address Register Field Name Type Description <31:0> PCI_ERR<31:0> RO PCI error.
A.2.5 Translated Base Registers 1 and 2 The translated base registers 1 and 2 provide the base address when mapping is enabled or disabled. The registers are shown in Figure A–21 and are defined in Table A–16. Figure A–21 Translated Base Registers 1 and 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 T_BASE<32:10> MBZ LJ-04198.AI Table A–16 Translated Base Registers 1 and 2 Field Name Type Description <31:9> T_BASE<32:10> RW Translated base.
A.2.6 PCI Base Registers 1 and 2 PCI base registers 1 and 2 provide the base address of the target window. The registers are shown in Figure A–22 and are defined in Table A–17. Figure A–22 PCI Base Registers 1 and 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PCI_BASE<31:20> WENB SGEN MBZ LJ-04199.AI Table A–17 PCI Base Registers 1 and 2 Field Name Type Description <31:20> PCI_BASE<31:20> RW PCI base.
A.2.7 PCI Mask Registers 1 and 2 PCI mask registers 1 and 2 define the size of the target window. The registers are shown in Figure A–23 and are defined in Table A–18. Figure A–23 PCI Mask Registers 1 and 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PCI_MASK<31:20> MBZ LJ-04200.AI Table A–18 PCI Mask Registers 1 and 2 Field Name Type Description <31:20> PCI_MASK<31:20> RW PCI mask.
A.2.8 Host Address Extension Register 0 The host address extension register is hardcoded to zero. A read transaction from this register returns zero; a write transaction has no effect. The register is shown in Figure A–24. Figure A–24 Host Address Extension Register 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Hardcoded to Zero LJ-04201.AI A.2.
A.2.10 Host Address Extension Register 2 The host address extension register 2 generates ad<31:24> on CPU-initiated transactions addressing PCI I/O space. It also generates ad<1:0> during PCI configuration read and write transactions. The register is shown in Figure A–26 and is defined in Table A–20. Figure A–26 Host Address Extension Register 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 EADDR<7:0> MBZ CONF_ADDR<1:0> LJ-04203.
A.2.11 PCI Master Latency Timer Register The PCI master latency timer register contains a value that determines the latency timer period. It should be programmed to be nonzero during system configuration. The register is shown in Figure A–27 and is defined in Table A–21. Figure A–27 PCI Master Latency Timer Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 MBZ PMLC<7:0> LJ-04204.
A.2.12 TLB Tag Registers 0 Through 7 The TLB tag registers contain the PCI page address associated with the CPU page address in the TLB data registers. The registers are shown in Figure A–28 and are defined in Table A–22. Figure A–28 TLB Tag Registers 0 Through 7 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PCI_PAGE<31:13> EVAL MBZ LJ-04205.AI Table A–22 TLB Tag Registers 0 Through 7 Field Name Type Description <31:13> PCI_PAGE<31:13> RO PCI page.
A.2.13 TLB Data Registers 0 Through 7 The TLB data registers contain the CPU page address associated with the PCI page address in the TLB tag registers. The registers are shown in Figure A–29 and are defined in Table A–23. Figure A–29 TLB Data Registers 0 Through 7 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 MBZ CPU_PAGE<32:13> MBZ LJ-04206.
B SROM Initialization The Alpha 21064A microprocessor provides a mechanism for loading the initial instruction stream (Istream) from a compact serial ROM (SROM) to start the bootstrap procedure. The SROM executable image is limited to the size of the CPU instruction cache (Icache). Because the image is running only in the Icache, it is relatively difficult to debug.
8. Scan the flash ROM for a special header that specifies where and how flash ROM firmware should be loaded. 9. Copy the contents of the flash ROM to memory and begin code execution. 10. Pass parameters up to the next level of firmware to provide a predictable firmware interface. B.1.1 Firmware Interface A firmware interface provides a mechanism for passing critical information about the state of the system and CPU up to the next level of firmware.
Table B–1 (Cont.) Output Parameter Descriptions Output Parameter Parameter Description r17 (a1) - Memory size This value is an unsigned quadword count of the number of contiguous bytes of good memory in the system starting at physical address zero. This simple mechanism will be sufficient for simple systems. Systems that need to communicate more detailed memory configuration may do so through the system context value (see last table entry).
Table B–1 (Cont.) Output Parameter Descriptions Output Parameter Parameter Description r20 (a4) - Active processor mask The processor mask identifies each processor that is present on the current system. Each mask bit corresponds to a processor number associated by the bit number (that is, bit 0 corresponds to processor 0). A value of 1 in the mask indicates that the processor is present; a value of 0 indicates that the processor is not present.
Table B–2 Cache Loop Delay Characteristics Function Minimum Delay Maximum Delay Description Tadr1 1.0 ns 1.6 ns Delay from CPU to input of address buffer Tbuf 1.0 ns 4.8 ns Buffer gate delay Tadr2 1.2 ns 1.5 ns Address delay from buffer to SRAM inputs 1 Tdat NA 1.9 ns Data return path from SRAM to CPU input pins Twe1 1.0 ns 1.0 ns Delay from CPU to the NOR gate in the WE path Tnor 1.2 ns 5.0 ns NOR gate delay Twe2 1.0 ns 1.
Table B–4 Worst-Case SRAM Timing Specifications Typical SRAM Timing Specifications 6-ns SRAM 8-ns SRAM 10-ns SRAM 12-ns SRAM 15-ns SRAM Tacc 6 ns 8 ns 10 ns 12 ns 15 ns Twc 6 ns 8 ns 10 ns 12 ns 15 ns Twp 6 ns 8 ns 9 ns 10 ns 12 ns Tdw 3 ns 4 ns 5 ns 6 ns 7 ns Tdh 0 ns 0 ns 0 ns 0 ns 0 ns Taw 6 ns 8 ns 9 ns 10 ns 12 ns Twr 0 ns 0 ns 0 ns 0 ns 0 ns Tas 0 ns 0 ns 0 ns 0 ns 0 ns Parameter Table B–5 CPU Specifications Function Specification Description Ts
Write Cycle Calculations WRsetup is the earliest from the beginning of a write cycle that the write pulse can be asserted (see Figure B–1). Figure B–1 Write Cycle Timing WRsetup WRpulse WRhold LJ-04207.AI W Rsetup = T adr1 + T buf + T adr2 + skew Taddress, based on the address path, and Tdata, based on the data path determine the earliest from the beginning of a write cycle that the write pulse can be deasserted.
B.1.5 Memory Initialization The memory banks must be configured such that they are naturally aligned. For example, a bank configured with 32MB must have a base address of zero or some multiple of 32MB. Therefore, to ensure that both banks are contiguous (no gaps), the larger bank should be set to a base of zero, and the smaller bank should be set to the address immediately following the last location in the larger bank. If the banks are the same size, this is still true.
B.1.6 L2 Cache Initialization These steps initialize L2 cache: 1. Set the BIU_CTL register in the CPU to ignore the L2 cache. 2. Set the general control register in the memory controller to enable the L2 cache while ignoring tag parity. 3. Clear the tag enable register in the memory controller. 4. Sweep the L2 cache with read transactions at cache block increments. 5. Reset the tag enable register with the proper value based on the L2 cache and memory size. 6.
B.1.7 Flash ROM (System ROM) The flash ROM, sometimes called the system ROM, is a 1MB, nonvolatile, writable ROM. After the SROM code initializes the AlphaPC64 system, flash ROM code prepares the system for booting. The flash ROM headers, structure, and access methods are described here. B.1.7.1 Special Flash ROM Headers The MAKEROM tool is used to place a special header on ROM image files. The SROM allows the flash ROM to contain several different ROM images, each with its own header.
Table B–6 describes each entry in the special header. Table B–6 Special Header Entry Descriptions Entry Description Validation and inverse validation pattern This quadword contains a special signature pattern used to validate that the special ROM header has been located. The pattern is 5A5AC3C3A5A53C3C. Header size (bytes) This longword contains the size of the header block, which varies among versions of the header specification.
Table B–6 (Cont.) Special Header Entry Descriptions Entry Description Firmware ID The firmware ID is a byte that specifies the firmware type. This information facilitates image boot options necessary to boot different operating systems.
Table B–7 Higher 512KB Flash ROM Image Selection TOY RAM Value1 Firmware ID2 Image Description 00 0 Evaluation board debug monitor firmware 01 1 Windows NT firmware 02 2 Alpha SRM firmware (OpenVMS)3 03 2 Alpha SRM firmware (Digital UNIX)3 4 8n NA SROM code will load the nth image from flash ROM. If n=0, the SROM code loads the entire flash ROM contents. If n=1,2, . . . , the SROM code loads the first image, second image, and so on. 1 Operating 2 Found system type.
Changing TOY RAM Location 3F—bootopt Debug Monitor Command Use the bootopt debug monitor command to change the value in location 3F. In the example shown here, the bootopt command is used to change the value in location 3F from 0 to 1. AlphaPC64> bootopt 1 Predefined bootoptions are... "0" "Alpha Evaluation Board Debug Monitor" "DBM" "1" "The Windows NT Operating System" "NT" "2" "OpenVMS" "VMS" "3" "DEC OSF/1" "OSF" O/S type selected: "Alpha Evaluation Board Debug Monitor" ....
B.1.7.3 Flash ROM Access The flash ROM can be viewed as two banks of 512KB each. At power-up the lower 512KB bank is accessed using the address range 3 FFF8 0000 to 3 FFFF FFFF. Setting address bit 19 will allow you to access the higher 512KB of flash ROM. Write a 1 to the register at address 800 to set address bit 19.
B.1.8 Icache Flush Code The following code is loaded into memory after the flash ROM image. It is then executed to flush the SROM initialization code from the Icache. The SROM initialization code is loaded into the Icache, and it maps to memory beginning at address zero. 77FF0055 mt r31, flushIc C0000001 br r0, +4 .
Figure B–3 J3 Connector (Repeated) sysclkdiv 1 2 jmp_irq2 3 4 jmp_irq1 5 6 jmp_irq0 7 8 toy_clr 9 10 sp_bit0 11 12 sp_bit1 13 14 sp_bit2 15 16 sp_bit3 17 18 sp_bit4 19 20 sp_bit5 21 22 sp_bit6 23 24 sp_bit7 25 26 gnd reset button 27 28 hd_act_l 29 30 hd_led_l 31 32 gnd spkr 33 34 key_lock vdd 35 36 gnd 37 38 gnd vdd 39 40 power_led_l To Speaker LJ-04132.
Table B–8 (Cont.) Jumper Position Descriptions (Repeated) Select Bit Register Bit Name sp_bit6 MINI_DEBUG Jumper out (default)—Boot selected image in flash ROM. Jumper in—Trap to SROM debug port (J1). sp_bit<5:3> BC_SPEED<2:0> L2 cache speed selection is shown here.
Table B–8 (Cont.) Jumper Position Descriptions (Repeated) Select Bit Register Bit Name Function sp_bit<2:0> BC_SIZE<2:0> L2 cache size selection is shown here.
C PCI Address Maps This appendix provides the AlphaPC64 PCI operating register address space maps. C.1 PCI Interrupt Acknowledge/Special Cycle Address Space The PCI interrupt acknowledge/special cycle address space comprises an address range from 1 B000 0000 through 1 BFFF FFFF. C.2 PCI Sparse I/O Address Space The PCI sparse I/O address space ranges from 1 C000 0000 to 1 DFFF FFFF. The PCI operating register set occupies this space. C.
Table C–1 (Cont.
Table C–1 (Cont.
Table C–1 (Cont.
Table C–1 (Cont.
C.5 SIO PCI-to-ISA Bridge Configuration Address Space Table C–3 is a map of SIO PCI-to-ISA bridge configuration address space. PCI address bit pci_ad19 drives the idsel chip select pin for access to the configuration register space.
Table C–3 (Cont.) SIO PCI-to-ISA Bridge Configuration Address Space Map Offset Address Register 80–81 1 E008 1008 BIOS timer base address register C.6 PCI Sparse Memory Address Space The PCI sparse memory address space comprises an address range from 2 0000 0000 through 2 7FFF FFFF. C.7 PCI Dense Memory Address Space The PCI dense memory address space comprises an address range from 3 0000 0000 through 3 FFFF FFFF. C.
Table C–4 PC87312 Combination Controller Register Address Space Map Address Offset Read/Write Physical Address Register 398 1 C000 7300 Index address register 399 1 C000 7320 Data address register Index Register General Registers 0 Function enable register 1 Function address register 2 Power and test register COM2 Serial Port Registers 2F8-R 0DLAB=0 1 C000 5F00 COM2 receiver buffer register 2F8-W 0DLAB=0 1 C000 5F00 COM2 transmitter holding register 2F8 0DLAB=1 1 C000 5F00 COM2 div
Table C–4 (Cont.
Table C–4 (Cont.
Table C–6 Utility Bus Device Decode Device Address Select Bits ecsen_l ecasaddr_2 ecasaddr_1 ecasaddr_0 Device Select Signal 0 0 0 0 rtcale_l TOY address 70, 72, 74, 76 0 0 0 1 rtccs_l TOY data 71, 73, 75, 77 0 0 1 0 kbcs_l Mouse/ Keyboard enable 60, 62, 64, 66 0 0 1 1 flashcs_l flash ROM enable1 — 0 1 0 0 — Unused — 0 1 0 1 — Unused — 0 1 1 0 — Unused — 0 1 1 1 — Unused — 1 0 0 0 — Unused — 1 0 0 1 — Unused — 1 0 1 0 — Unused
C.10 Interrupt Control PLD Addresses Table C–7 lists the registers and memory addresses for the interrupt control PLD. Table C–7 Interrupt Control PLD Addresses Offset Physical Address Register 804 1 C001 0080 Interrupt status/interrupt mask register 1 805 1 C001 00A0 Interrupt status/interrupt mask register 2 806 1 C001 00C0 Interrupt status/interrupt mask register 3 C.
Table C–9 Time-of-Year Clock Device Addresses Offset Index Latched Physical Address Register 70 0 1 C000 0E00 Seconds 70 1 1 C000 0E00 Seconds alarm 70 2 1 C000 0E00 Minutes 70 3 1 C000 0E00 Minutes alarm 70 4 1 C000 0E00 Hour 70 5 1 C000 0E00 Hour alarm 70 6 1 C000 0E00 Day of week 70 7 1 C000 0E00 Day of month 70 8 1 C000 0E00 Month 70 9 1 C000 0E00 Year 70 A 1 C000 0E00 Register A 70 B 1 C000 0E00 Register B 70 C 1 C000 0E00 Register C 70 D 1 C000
C.13.1 Flash Memory Segment Select Register Table C–10 lists the register address for the flash ROM. The flash ROM is partitioned into two 512KB segments. Write a value of 0 to ISA address 800 to select the lower 512KB. Write a value of 1 to ISA address 800 to select the higher 512KB. This register is write-only. Table C–10 Flash Memory Segment Select Register Offset Physical Address Register 800 1 C001 0000 Flash segment select C.13.
Table C–12 Flash ROM Configuration Registers Offset Data Written on First Access Register X1 FF Read array/reset register X 90 Intelligent identifier register X 70 Read status register 50 Clear status register 20 Erase setup/confirm register X B0 Erase suspend/resume register WA3 40 Byte write setup/write register WA 10 Alternate byte write setup/write register X BA 1X 2 = Any byte within the flash ROM address range. 2 BA = Target address within the block being erased.
Table C–13 Memory Map of Flash Memory Offset Physical Address Block Number1 Capacity 0 0000– 3 FFF8 0000– 0,8 64KB 0 FFFF 3 FFF8 FFFF 1 0000– 3 FFF9 0000– 1,9 64KB 1 FFFF 3 FFF9 FFFF 2 0000– 3 FFFA 0000– 2,10 64KB 2 FFFF 3 FFFA FFFF 3,11 64KB 4,12 64KB 5,13 64KB 6,14 64KB 7,15 64KB 3 0000– 3 FFFB 0000– 3 FFFF 3 FFFB FFFF 4 0000– 3 FFFC 0000– 4 FFFF 3 FFFC FFFF 5 0000– 3 FFFD 0000– 5 FFFF 3 FFFD FFFF 6 0000– 3 FFFE 0000– 6 FFFF 3 FFFE FFFF 7 0000– 3 FFFF 0000–
D Technical Support and Ordering Information D.1 Technical Support If you need technical support or help deciding which literature best meets your needs, call the Digital Semiconductor Information Line: United States and Canada Outside North America 1–800–332–2717 +1–508–628–4760 D.2 Ordering Alpha Microprocessor Sample Kits To order an Alpha microprocessor Sample Kit, which contains one Alpha microprocessor, one heat sink, and supporting documentation, call 1–800–DIGITAL.
D.3 Ordering Digital Semiconductor Products To order the AlphaPC64 evaluation board and related products, contact your local distributor.
D.4 Ordering Associated Literature The following table lists some of the available Digital Semiconductor literature. For a complete list, contact the Digital Semiconductor Information Line.
D.
Index 21071-BA functional description, 3–20 BA error checking, 3–22 DMA write buffer, 3–22 epiData bus, 3–21 I/O read and merge buffer, 3–21 I/O write and DMA read buffer, 3–21 memData bus, 3–21 memory read buffer, 3–21 memory write buffer, 3–22 sysData bus, 3–20 overview, 3–7 21071-CA CSR descriptions, A–1 to A–24 See also specific register entries CSR space, 4–5 functional description, 3–8 address decoding, 3–10 CA error handling, 3–10 L2 cache control, 3–9 sysBus arbitration, 3–9 sysBus controller, 3–10
B BA error checking, 3–22 Bank set timing register A, A–17 Bank set timing register B, A–17 Base address registers, A–12 Bit notation, xvii Board configuration, 2–1 Board connectors, 2–6 Board layout, 1–6 Board overview, 1–1 Board uses, 1–6 Bridge See SIO PCI-to-ISA bridge C CA error handling, 3–10 Cacheable memory space, 4–4 Cautions, xvii Chipset overview, 3–1 DECchip 21071-BA, 3–7 DECchip 21071-CA, 3–2 DECchip 21071-DA, 3–4 Chipset support, 1–2 Clock subsystem, 3–24 14.
F Features, 1–1 Flash ROM, 3–43, B–10 access, B–15 address bit 19, B–15 banks, B–12 enable/disable jumpers, 2–6 header content, B–10 higher bank image selection, B–12 MAKEROM tool, B–10 operating systems, 3–43 special headers, B–10 structure, B–12 TOY RAM location 3F, B–13 update-enable jumper, B–15 G General control register, A–1 Global timing register, A–22 Graphics interface, 3–34 Guaranteed access-time mode, 3–19 H Handling errors with error address register locked, 3–23 Hardware configuration jumpers
Memory controller, 3–11 memory address generation, 3–11 memory organization, 3–11 memory page mode support, 3–11 presence detect logic, 3–12 programmable memory timing, 3–12 read latency minimization, 3–11 transaction scheduler, 3–12 Memory figures, xv Memory organization, 3–11 Memory page mode support, 3–11 Memory read buffer, 3–21 Memory subsystem, 1–2 Memory write buffer, 3–22 Must be zero, xv N Noncacheable memory space, 4–4 Numbering, xiv O Operating systems, 3–43 debug and monitor code, 3–43 serial
Physical board parameters, 5–2 Power distribution, 3–39 Power requirements, 5–1 See also Power distribution Presence detect high-data register, A–12 Presence detect logic, 3–12 Presence detect low-data register, A–11 Processor interrupts, 3–19 Programmable array logic, 1–2 Programmable memory timing, 3–12 R Ranges, xv Read latency minimization, 3–11 References See Schematic references Refresh timing register, A–23 Register field notation, xvi Register figures, xv Registers, A–1 to A–38 See also specific re
System software (cont’d) software support, 1–5 Translation buffer invalidate all register, A–38 T U Tag enable register, A–6 Technical support, D–1 Time-of-year clock See TOY clock TLB data registers 0 through 7, A–38 TLB tag registers 0 through 7, A–37 TOY clock, 3–37 Transaction scheduler, 3–12 Translated base register 1, A–31 Translated base register 2, A–31 Ubus, 1–4 address decode, C–10 memory devices, 3–37 UNDEFINED, xiv UNPREDICTABLE, xiv Utility bus See Ubus V Video frame pointer register, A–1
