User guide

10.2.3 Interprocessor Communication ................... 10–14
10.2.3.1 Interprocessor Communication Registers . . ...... 10–14
10.2.3.2 Interprocessor Communication Global Switches. . . 10–14
10.2.3.3 Interprocessor Communication Module
Switches . . ............................... 10–15
10.3 System Controller Operation ....................... 10–17
10.3.1 Arbitrating the VMEbus ....................... 10–18
10.3.1.1 Requesting the VMEbus..................... 10–18
10.3.1.2 Releasing the VMEbus ...................... 10–19
10.3.2 System Clock Output . . . ....................... 10–21
10.3.3 Timeout Timers .............................. 10–21
10.3.3.1 Arbitration Timers . . ....................... 10–21
10.3.3.2 VMEbus Transfer Timers .................... 10–22
10.3.3.3 Local Bus Transfer Timer ................... 10–23
10.3.4 VMEbus Interrupt Handling .................... 10–23
10.4 Byte Swapping . . . ............................... 10–26
10.4.1 DC7407 Byte Swapping . ....................... 10–26
10.4.2 VIC64 Byte Swapping . . ....................... 10–27
10.5 Initializing the VME Interface ...................... 10–30
10.5.1 VME PCI Configuration Registers . ............... 10–30
10.5.2 Programming Scatter-Gather RAM ............... 10–31
10.5.3 Configuring the VIC64 . . ....................... 10–32
10.6 Summary of VME Interface Registers . ............... 10–37
10.7 VME Subsystem Restrictions (as of 03-Jun-94) . . . ...... 10–40
10.7.1 Collision of VIC64 Master Write Posting with Master
Block Transfers .............................. 10–40
10.7.2 VIC64 Errata: A16 Master Cycles During
Interleave................................... 10–40
11 System Interrupts
11.1 System Interrupts ............................... 11–1
11.1.1 Xilinx Interrupt Controller...................... 11–2
11.1.2 VIC64 Chip System Interrupt Controller ........... 11–4
11.1.2.1 Basic Operation ........................... 11–5
11.1.3 VIC64 Chip Interrupt Sources ................... 11–6
11.1.3.1 Local Device Interrupts ..................... 11–6
11.1.3.2 VMEbus Interrupt Requests . . ............... 11–7
11.1.3.3 Status/Error Interrupts ..................... 11–8
11.1.4 SIO Chip Programmable Interrupt Controller . ...... 11–11
11.1.4.1 Nonmaskable System Events . . ............... 11–11
11.1.4.2 NMI Status and Control Register ............. 11–12
11.1.4.3 EPIC Interrupt ........................... 11–13
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