User guide

Interval Timer Tests
Interval Timer Tests
The interval timer tests test the functionality of the 8254 interval timer chip and
surrounding external circuitry, including latches, programmable-array logic (PAL)
devices and printed circuit board module etch.
Since all three interval timers of the 8254 chip have different external
configurations, several tests are required for complete test coverage.
The intent of the tests is to verify that timers 0, 1, and 2 can generate a CPU
interrupt, if properly enabled, at the programmed frequency.
These tests require that you properly program both timer 0 and 1 and connect
them externally for successful operation.
Timer 2 Terminal Count Test
This test exercises Timer 2 with the timer interrupts enabled. In the Digital
Alpha VME 4 design, the gate input for Timer 2 is always enabled and the clock
input is connected to a 10 MHz (100 ns period) clock source.
Timer 2 is programmed to mode 0, interrupt on terminal count. After the timer is
initially programmed to mode 0 and loaded with a count value, the OUT output is
low and remains low until the internal count value reaches zero. When the count
value reaches zero, OUT output is asserted high and remains high until timer
2 is reprogrammed. The event of OUT transitioning from low to high should
generate a CPU interrupt.
The interrupt service routine (ISR) invoked due to the timer generated interrupt
sets a global flag indicating the interrupt took place and that software was
dispatched to the correct point.
Console Command: i8254_diag -t 1
Miscellaneous Notes
• The interrupt enable bits for timers 0 and 2 (bits 4 and 5 of the interrupt
status register at address 0x4010) are not writable directly. Bit 4 is toggled
by writing to address 0x4010; bit 5 is toggled by writing to address 0x4014.
In both cases, the data written is Don’t Care.
• A read of the interrupt status register at address 0x4014 causes both
interrupt status bits (bits 0 and 1) to be cleared.
• Due to hardware limitations on interrupt detection, the value programmed
into timer 2 must be greater than 2.
4–10 Diagnostics