User guide

POST Memory Diagnostic
POST Memory Diagnostic
The POST memory diagnostic test verifies system memory. It runs with ECC
enabled. If the test detects a memory error that cannot be corrected with ECC, it
logs the error in the error logging area of NVRAM.
Description
See also memtest in Chapter 13.
Note
This test is dependent upon the setting of the console MODE environment
variable. Setting mode to FASTBOOT evokes a quick verify test of the
memory, and NOFASTBOOT evokes a full test of memory.
This test executes at the beginning of console boot before the console drivers and
devices have been initialized.
This test provides the following coverage:
Memory bits Stuck bits, bit transition fault, or bit
coupling fault.
Decoder logic An address selects no memory, two or
more addresses select the same memory
cell, or one address selects more than one
cell.
Sense amplifier logic Stuck fault or coupling fault.
Component and path coverage The CPU memory control logic, etch from
the CPU to the daughter card connectors,
etch from the CPU backup cache control
to the backup cache and from backup
cache to the memory bus. The daughter
card is assumed good since it is tested
separately in manufacturing.
Test Name: None; executes on power-on.
Diagnostics 4–7