User guide
6.5 Address Space of Control/Status Registers ............. 6–8
6.6 Description of CSRs .............................. 6–11
6.6.1 General Control Register ....................... 6–11
6.6.2 Error and Diagnostic Status Register ............. 6–13
6.6.3 Tag Enable Register ........................... 6–16
6.6.4 Error Low Address Register ..................... 6–18
6.6.5 Error High Address Register .................... 6–19
6.6.6 LDx_L Low Address Register .................... 6–19
6.6.7 LDx_L High Address Register ................... 6–20
6.6.8 Memory Control Registers ...................... 6–20
6.6.8.1 Presence Detect Low-Data Register ............ 6–20
6.6.8.2 Presence Detect High-Data Register ........... 6–21
6.6.8.3 Base Address Registers ..................... 6–21
6.6.8.4 Configuration Registers ..................... 6–22
6.6.8.5 Bank Set Timing Registers . . . ............... 6–24
6.6.8.6 Global Timing Register ..................... 6–27
6.6.8.7 Refresh Timing Register .................... 6–28
6.7 Data Path ..................................... 6–30
6.7.1 Memory Read Buffer . . . ....................... 6–31
6.7.2 I/O Read Buffer and Merge Buffer . ............... 6–31
6.7.3 I/O Write and DMA Read Buffer . . ............... 6–31
6.7.4 DMA Write Buffer ............................ 6–31
6.7.5 Memory Write Buffer . . . ....................... 6–32
6.7.6 Error Handling .............................. 6–32
7 PCI Host Bridge
7.1 Interface to the System Bus . ....................... 7–2
7.1.1 Decoding Physical Addresses .................... 7–2
7.1.2 Buffering System Bus Transactions ............... 7–3
7.1.3 Burst Length and Prefetching for the System Bus .... 7–3
7.2 Interface to the PCI bus ........................... 7–3
7.2.1 Decoding PCI Addresses ....................... 7–3
7.2.2 Buffering PCI Transactions ..................... 7–3
7.2.3 Burst Length and Prefetching for PCI bus .......... 7–4
7.3 Features ....................................... 7–4
7.3.1 Burst Order . . ............................... 7–4
7.3.2 Parity Support .............................. 7–4
7.3.3 Data Coherency .............................. 7–5
7.3.4 Interrupts . . . ............................... 7–6
7.3.5 Exclusive Access ............................ 7–6
7.3.6 Bus Parking . . ............................... 7–6
7.3.7 Retry Timeout ............................... 7–7
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