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5 System Address Mapping
5.1 CPU Address Mapping to PCI Space . . ............... 5–1
5.1.1 Cacheable Memory Space (0x000000000 to
0x0FFFFFFFF) .............................. 5–4
5.1.2 Noncacheable Memory Space (0x100000000 to
0x17FFFFFFF) .............................. 5–4
5.1.3 DECchip 21071-CA CSR Space (0x180000000 to
0x19FFFFFFF) .............................. 5–4
5.1.4 DECchip 21071-DA CSR Space (0x1A0000000 to
0x1AFFFFFFF) .............................. 5–5
5.1.5 PCI Interrupt Acknowledge/Special Cycle Space
(0x1B0000000 to 0x1BFFFFFFF) . . ............... 5–5
5.1.6 PCI Sparse I/O Space (0x1C0000000 to
0x1DFFFFFFF) .............................. 5–5
5.1.7 PCI Configuration Space (0x1E0000000 to
0x1FFFFFFFF) .............................. 5–8
5.1.7.1 PCI Configuration Cycles to Primary Bus
Targets . . . ............................... 5–9
5.1.7.2 PCI Configuration Cycles to Secondary Bus
Targets . . . ............................... 5–10
5.1.8 PCI Sparse Memory Space (0x200000000 to
0x2FFFFFFFF) .............................. 5–11
5.1.9 PCI Dense Memory Space (0x300000000 to
0x3FFFFFFFF) .............................. 5–14
5.2 PCI-to-Physical Memory Addressing . . ............... 5–15
6 Cache and Memory Subsystem
6.1 System Bus Interface ............................. 6–4
6.1.1 Arbitration on the System Bus................... 6–4
6.1.2 System Bus Controller . . ....................... 6–4
6.1.3 Decoding Addresses ........................... 6–4
6.2 Bcache Control . . . ............................... 6–5
6.3 Memory Controller ............................... 6–5
6.3.1 Memory Organization . . ....................... 6–6
6.3.2 Memory Address Generation .................... 6–7
6.3.3 Support for Memory Page Mode . . ............... 6–7
6.3.4 Minimizing Read Latency ...................... 6–7
6.3.5 Transaction Scheduler . . ....................... 6–7
6.3.6 Programmable Memory Timing . . . ............... 6–7
6.3.7 Presence Detect Logic . . ....................... 6–8
6.4 Error Handling . . ............................... 6–8
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