User guide

O
Operating system, booting, 3–7
> operator, 12–12
Operators
redirection operator, 12–12
shell, 12–3
Order numbers, 2–35
P
Page monitor CSR, 10–13
PAL
devices, testing, 4–10
environment variable, 3–6
Parallel interface, 1–2
Parallel port connector pinouts, A–8
Parity support, for PCI devices, 7–4
PCI bus, 8–1
addresses, decoding, 7–3
base registers, 5–15, 7–16
configuration address space, 5–8
decoding for primary bus
configuration addresses in,
5–8
definition of, 5–8
configuration registers, 8–3, 8–7
control register, 9–3
cycles, 8–5
dense memory address space, 5–14
direct mapped target address
translation for, 5–17
error address register, 7–13
expansion, 1–2
I/O subsystem components, 8–2
interface to, 7–3
interrupt acknowledge/special cycle
address space, 5–5
mapping memory pages from VMEbus,
10–10
mask registers, 5–15, 7–17
master latency timer register, 7–20
master timeout for, 7–7
parking on, 7–6
PCI bus (cont’d)
primary
address space of, 5–8
configuration cycles to targets of,
5–9
scatter-gather map
address for, 5–19
page table entry in memory for,
5–18
translation to system bus address,
5–21
secondary, address space of, 5–8
sparse I/O address space, 5–5
byte enable generation of, 5–7
translation of, 5–6
sparse memory address space, 5–11
generation of addresses for, 5–14
generation of byte enable for, 5–13
translation of, 5–11
target window compare scheme for,
5–16
target window enables of, 5–15
transactions, buffering, 7–3
translated base register, 5–15
uses with Digital Alpha VME 4, 1–1
PCI host bridge, 7–1
burst length, 7–3, 7–4
burst order, 7–4
bus parking, 7–6
CSRs, 7–9
address space of, 7–7
decoding physical addresses, 7–2
exclusive access protocol, 7–6
features, 7–4
interrupts for CPU, 7–6
iogrant signal, 7–6
locking access to main memory for,
7–6
parity support for devices, 7–4
retry timeout, 7–7
synchronization with CPU, 7–5
write transactions, 7–3, 7–4
PCI I/O companion card, 8–11
Index–11