User guide

Index
A
ACFAIL* assertion, 11–8
Address mapping, 5–1
Address modifier, 10–6
Address space
cacheable, 5–4
DECchip 21071-CA CSR, 5–4
DECchip 21071-DA, 7–7
DECchip 21071-DA CSR, 5–5
noncacheable, 5–4
of Nbus, 9–1
of PCI dense memory space, 5–14
of PCI host bridge CSRs, 7–7
of super I/O chip, 9–2
of super I/O register, 9–19
of VME interface, 10–2
PCI configuration, 5–8
decoding for primary bus
configuration addresses in,
5–8
definition of, 5–8
PCI interrupt acknowledge/special cycle
in, 5–5
PCI sparse I/O, 5–5
byte enable generation of, 5–7
translation of, 5–6
PCI sparse memory, 5–11
generation of addresses for, 5–14
generation of byte enable for, 5–13
translation of, 5–11
Addresses
of keyboard/mouse controller, 9–22
of PCI bus, decoding, 7–3
Addresses (cont’d)
physical, decoding of by PCI host
bridge, 7–2
stepping in configuration cycles, 7–7
VME interface, decoding, 10–10
alloc command, 13–4
Alpha VME CPU
See Digital Alpha VME 4
Arbitration timeout, 11–8
Arbitration timers, 10–21
Arrow keys, 13–2
AUTO_ACTION environment variable,
3–4
Auxiliary terminal, connecting, 2–21
B
Background, running commands in,
12–13
Backspace key, 13–1
Bank setting registers, 6–24
Base address registers, 6–21
Bcache, 6–2
Bcache configuration register, 9–16
Bcache controller, 6–5
Blank panels, inserting, 2–22
Block mode data transfers, 10–7
boot command, 13–6
BOOTDEF_DEV environment variable,
3–4
BOOTED_DEV environment variable,
3–4
Index–1