User guide

The VMEbus SYSRESET* assertion generates a module reset only if Switch 3
is closed. This prevents a module configured as a VME system controller from
locking into a reset state when it issues a VME SYSRESET* under software
control.
If Switch 3 is open, the VIC64 chip still resets (all internal registers return to
their default state, current transactions are aborted) but the module reset is not
generated. To allow detection of this condition (VIC64 chip only reset), the VME
SYSRESET* signal is tied to interrupt and interrupt mask register 3<0>.
11–14 System Interrupts