User guide

Table 11–4 (Cont.) NMI Status and Control Register Bits
Field Name Type Description
<3> HALT Enable R/W When set to a one, HALTs are disabled and the
halt status bit in this register is cleared. When
cleared (reset default), HALTs are enabled as
NMI events.
<2> SERR Enable R/W When set to a 1, SERR reporting is disabled and
the SERR status bit in this register is cleared.
When cleared (reset default), SERRs are enabled
as NMI events.
<1:0> - R/W Ignore on read. Writes must be 0.
Note
The SIO chip specification specifies that HALT events are reported by the
SIO chip’s IOCHK# pin.
11.1.4.3 EPIC Interrupt
The 21071-DA interrupts the CPU using the int_hw0 signal when there are
errors to report. The 21071-DA chip does not distinguish between hard and soft
errors when asserting the interrupt signal.
The 21071-DA chip responds to CPU read block commands directly to the
interrupt acknowledge address space, which triggers the 21071-DA chip to
perform an interrupt acknowledge transaction on the PCI bus. The interrupt
vector returned on the PCI bus is returned to the CPU through the sysBus by the
21071-DA chip.
11.2 Module Reset
The Digital Alpha VME 4 module can be reset by four distinct events:
• Power-up
• Front panel switch
• Watchdog timeout
• VMEbus SYSRESET* assertion (if enabled)
All on-board logic, except the module-level reset reason register, are hardware
reset by all of these reset events.
System Interrupts 11–13